MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 352

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

DSCR — Development Support Control Register
8.4.2 TPU3 Test Configuration Register
TCR — TPU3 Test Configuration Register
8.4.3 Development Support Control Register
MC68F375
REFERENCE MANUAL
HOT4
Bit(s)
MSB
Bit(s)
14:11
15
3:0
8:7
15
10
0
4
9
6
5
RESET:
Used for factory test only.
14
IARB[3:0]
T2CSL
Name
Name
HOT4
CLKS
BLC
FRZ
CCL
BP
—
RESERVED
13
TCR2 counter clock edge. This bit and the T2CG control bit determine the clock source for TCR2.
Refer to
Interrupt Arbitration ID. The IARB field is used to arbitrate between simultaneous interrupt
requests of the same priority. Each module that can generate interrupt requests must be
assigned a unique, non-zero IARB field value.
Hang on T4
0 = Exit wait on T4 state caused by assertion of HOT4
1 = Enter wait on T4 state
Reserved
Branch latch control
0 = Latch conditions into branch condition register before exiting halted state
1 = Do not latch conditions into branch condition register before exiting the halted state or during
Stop clocks (to TCRs)
0 = Do not stop TCRs
1 = Stop TCRs during the halted state
FREEZE assertion response. The FRZ bits specify the TPU microengine response to the IMB3
FREEZE signal
00 = Ignore freeze
01 = Reserved
10 = Freeze at end of current microcycle
11 = Freeze at next time-slot boundary
Channel conditions latch. CCL controls the latching of channel conditions (MRL and TDL) when
the CHAN register is written.
0 = Only the pin state condition of the new channel is latched as a result of the write CHAN reg-
1 = Pin state, MRL, and TDL conditions of the new channel are latched as a result of a write
0 = Breakpoint not enabled
1 = Break if PC equals PC breakpoint register
PC breakpoint enable
12
Table 8-6 TPUMCR Bit Settings (Continued)
the time-slot transition period
ister microinstruction
CHAN register microinstruction
Freescale Semiconductor, Inc.
8.3.9 Prescaler Control for TCR2
11
For More Information On This Product,
Table 8-7 DSCR Bit Settings
BLC
10
0
TIME PROCESSOR UNIT 3
Go to: www.freescale.com
CLKS
9
0
Rev. 25 June 03
8
0
FRZ
7
0
Description
Description
for details.
CCL
6
0
BP
5
0
BC
4
0
0x30 4002, 0x30 4402
BH
3
0
BL
2
0
0xYF FE04
MOTOROLA
BM
1
0
LSB
8-12
BT
0
0