MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 359

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
Bit(s)
15:9
6:5
4:2
8
7
1
0
SOFT RST
ETBANK
FPSCK
Name
DTPU
T2CF
DIV2
—
Reserved
Divide by 2 control. When asserted, the DIV2 bit, along with the TCR1P bit and the PSCK bit in
the TPUMCR, determines the rate of the TCR1 counter in the TPU3. If set, the TCR1 counter
increments at a rate of two system clocks. If negated, TCR1 increments at the rate determined
by control bits in the TCR1P and PSCK fields.
0 = TCR1 increments at rate determined by control bits in the TCR1P and PSCK fields of the
1 = Causes TCR1 counter to increment at a rate of the system clock divided by two
Soft reset. The TPU3 performs an internal reset when both the SOFT RST bit in the TPUMCR2
and the STOP bit in TPUMCR are set. The CPU must write zero to the SOFT RST bit to bring
the TPU3 out of reset. The SOFT RST bit must be asserted for at least nine clocks.
0 = Normal operation
1 = Puts TPU3 in reset until bit is cleared
NOTE: Do not attempt to access any other TPU3 registers when this bit is asserted. When this
bit is asserted, it is the only accessible bit in the register.
Entry table bank select. This field determines the bank where the microcoded entry table is situ-
ated. After reset, this field is 0b00. This control bit field is write once after reset. ETBANK is used
when the microcode contains entry tables not located in the default bank 0. To execute the ROM
functions on this MCU, ETBANK[1:0] must be 00. Refer to
NOTE: This field should not be modified by the programmer unless necessary because of cus-
tom microcode.
Filter prescaler clock. The filter prescaler clock control bit field determines the ratio between sys-
tem clock frequency and minimum detectable pulses. The reset value of these bits is zero,
defining the filter clock as four system clocks. Refer to
T2CLK pin filter control. When asserted, the T2CLK input pin is filtered with the same filter clock
that is supplied to the channels. This control bit is write once after reset.
0 = Uses fixed four-clock filter
1 = T2CLK input pin filtered with same filter clock that is supplied to the channels
Disable TPU3 pins. When the disable TPU3 control pin is asserted, pin TP15 is configured as an
input disable pin. When the TP15 pin value is zero, all TPU3 output pins are three-stated, regard-
less of the pins function. The input is not synchronized. This control bit is write once after reset.
0 = TP15 functions as normal TPU3 channel
1 = TP15 pin configured as output disable pin. When TP15 pin is low, all TPU3 output pins are
TPUMCR register
in a high-impedance state, regardless of the pin function.
Freescale Semiconductor, Inc.
Table 8-18 Entry Table Bank Location
For More Information On This Product,
Table 8-17 TPUMCR2 Bit Settings
TIME PROCESSOR UNIT 3
Go to: www.freescale.com
ETBANK
00
01
10
11
Rev. 25 June 03
Description
Bank
0
1
2
3
Table
Table
8-19.
8-18.
MOTOROLA
8-19