MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 253

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

SPCR3 — QSPI Control Register 3
SPCR2 — QSPI Control Register 2
6.7.1.4 QSPI Control Register 3
MC68F375
REFERENCE MANUAL
RESET:
MSB
SPIFIE WREN WRTO
Bit(s)
12:8
MSB
15
7:5
4:0
15
14
13
0
15
RESET:
0
SPCR3 contains the loop mode enable bit, halt and mode fault interrupt enable, and
the halt control bit. The CPU has read/write access to SPCR3, but the QSPI has read
access only. SPCR3 must be initialized before QSPI operation begins. Writing a new
value to SPCR3 while the QSPI is enabled disrupts operation.
*See bit descriptions in
14
0
NEWQP
14
ENDQP
SPIFIE
0
WREN
WRTO
Name
RESERVED
—
13
0
13
0
SPI finished interrupt enable. Refer to
0 = QSPI interrupts disabled
1 = QSPI interrupts enabled
Wrap enable. Refer to
0 = Wraparound mode disabled.
1 = Wraparound mode enabled.
Wrap to. When wraparound mode is enabled and after the end of queue has been reached,
WRTO determines which address the QSPI executes next. The end of queue is determined by
an address match with ENDQP.
0 = Wrap to pointer address 0x0
1 = Wrap to address in NEWQP
Ending queue pointer. This field determines the last absolute address in the queue to be com-
pleted by the QSPI. After completing each command, the QSPI compares the queue pointer
value of the just-completed command with the value of ENDQP. If the two values match, the
QSPI sets SPIF to indicate it has reached the end of the programmed queue. Refer to
Operation
Reserved
New queue pointer value. This field contains the first QSPI queue address. Refer to
Operation
12
0
12
0
Table
Freescale Semiconductor, Inc.
11
QUEUED SERIAL MULTI-CHANNEL MODULE
0
11
For More Information On This Product,
0
for more information.
for more information.
6-18.
Table 6-16 SPCR2 Bit Settings
LOOP
ENDQP
10
Q
0
10
0
Go to: www.freescale.com
6.7.5.7 Master Wraparound
HMIE
9
0
9
0
Rev. 25 June 03
HALT
8
0
8
0
6.7.4.2 QSPI
7
7
0
Description
RESERVED
6
6
0
Interrupts.
Mode.
5
5
0
4
4
0
SPSR*
3
3
0
NEWQP
2
2
0
0xYF FC1C
0xYF FC1E
MOTOROLA
6.7.4 QSPI
1
0
1
6.7.4 QSPI
LSB
LSB
6-19
0
0
0