MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 90

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.3.3 Slow Reference Mode
MC68F375
REFERENCE MANUAL
The filter for both PLL modes consists of resistor R1 connected in series with capacitor
C1. This combination is connected between V
C2, is also connected between V
The following sections describe the clock sub-module in detail. One rule applies to all
modes of operation — the actual VCO core frequency must stay at or below two times
the maximum allowable system clock frequency. When changing frequencies, ensure
that the values written to the W, X, and Y bits do not select VCO core frequencies
above that value. If a system clock frequency is to be changed with multiple writes to
SYNCR, the write sequences should select lower VCO core frequencies first, and the
higher VCO core frequencies last unless it is certain the write sequence will not result
in VCO core frequencies above the maximum allowable system clock frequency.
In slow reference mode, the system clock is generated by the PLL typically from a
32.768-KHz reference. The frequency of the system clock is controlled by program-
ming the X, Y, and W bits according to
The W bit is in the feedback path of the VCO. When clear, this bit multiplies the refer-
ence frequency by two, and when set, by eight. This bit is clear at reset.
The Y bit divider is a 6-bit modulo counter which can multiply the reference input fre-
quency by up to 256, providing a large number of programmable system clock
frequencies. The Y bits are all set to one at reset, providing the highest frequency sys-
tem clock for a given combination of X and W bits.
The X bit is in the output path of the VCO. It may be used to divide the system clock
by two when clear and pass it without dividing when set. At reset, this bit is cleared to 0.
In slow reference mode, the W and Y bits are both in the feedback path of the PLL.
Changing the value of these bits requires the PLL to relock (with some delay) at the
new frequency. Changing the X bit, however, will change the system clock frequency
without having to wait for the PLL to relock.
Note that for slow reference mode, the crystal is not constrained to be 32.768 KHz but
must be in the range of 25 KHz to 50 KHz to ensure that the on-chip crystal oscillator
will work.
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
DDSYN
Rev. 25 June 03
Table
and XFC.
4-6.
DDSYN
and XFC. A second capacitor,
MOTOROLA
4-8