MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 153

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.8.3 Interrupt Acknowledge and Arbitration
MC68F375
REFERENCE MANUAL
IRQ[6:1] are maskable. IRQ7 is non-maskable. The IRQ7 input is transition sensitive
to prevent redundant servicing and stack overflow. A non-maskable interrupt is gener-
ated each time IRQ7 is asserted and each time the CCR is written while IRQ7 is
asserted. A write to the CCR re-arms the IRQ7 detection circuitry; consequently, any
write to the CCR while IRQ7 is asserted, even one that sets the IP field to 0b111, will
generate a new IRQ7 interrupt.
Interrupt requests are sampled on consecutive falling edges of the system clock. Inter-
rupt request input circuitry has hysteresis. To be valid, a request signal must be
asserted for at least two consecutive clock cycles. Valid requests do not cause imme-
diate exception processing, but are left pending. Pending requests are processed at
instruction boundaries or when processing of higher priority exceptions is complete.
The CPU32 does not latch the priority of pending interrupt requests. If an interrupt
source of higher priority makes a request while a lower priority request is pending, the
higher priority request will be serviced. If an interrupt request with a priority less than
or equal to the current IP mask value is made, the CPU32 will not recognize the
request. If simultaneous interrupt requests of different priorities are made, and both
have a priority greater than the mask value, the CPU32 will recognize the higher pri-
ority request.
When the CPU32 detects one or more interrupt requests of a priority higher than the
IP mask value, a read cycle from address 0b11111111111111111111: [IP]:1 in CPU
space is executed. Refer to
for more information.
The CPU space read cycle performs two functions. It places a mask value correspond-
ing to the highest priority interrupt request on the address bus, and it acquires an
exception vector number from the interrupt source. The mask value is decoded by
modules or external devices that have requested interrupt service to determine
whether the current interrupt acknowledge (IACK) cycle pertains to them. It is also
latched into the IP field to mask lower priority interrupts during exception processing.
Modules that have requested interrupt service decode the IP value placed on the
address bus at the beginning of the IACK cycle, and if their requests are at the speci-
fied IP level, respond to the cycle. Arbitration between simultaneous requests of the
same priority is performed by serial contention between module interrupt arbitration
(IARB) field bit values.
Each module that can request interrupt service, including the SCIM2E, has an IARB
field in its module configuration register. To implement an arbitration scheme, each
module that can request interrupt service must be assigned a unique, non-zero IARB
field value during system initialization. Arbitration priorities can range from 0b0001
(lowest) to 0b1111 (highest). If the CPU32 recognizes an interrupt request from a mod-
ule that has an IARB field value of 0b0000, a spurious interrupt exception will be
processed.
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
For More Information On This Product,
4.5.1.7 Function Codes
Go to: www.freescale.com
Rev. 25 June 03
and
4.6.4 CPU Space Cycles
MOTOROLA
4-71