MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 51

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

2.2 Pinout
2.2.1 Pinout Diagram
MC68F375
REFERENCE MANUAL
Instruction Pipeline
Interrupt Request Level
QADC64 Multiplexed Ad-
dress
Master-In Slave-Out
Master-Out Slave-In
Peripheral Chip Select
QADC64 Port A
QADC64 Port B
Quotient Out
Read/Write
Reset
Read-Modify-Write Cycle
SCI Receive Data
QSPI Serial Clock
Size
Slave Select
TPU3 Clock
TPU3 I/O Channels
Three-State Control
SCI Transmit Data
Clock Mode Select
CMFI Block 0 Program/
Erase Enable
External Filter Capacitor
The production MC68F375 will be bumped flip-chip and PBGA.
The pad numbers for each pad/signal on the die are shown in
the numbers and names correspond to the pad names and order on the die. The pin/
bump numbers on the PBGA and Bumped die may be different. The chip layout plan
is also shown in
Signal Name
Figure
VDDSYN/MODCLK Selects the source of the internal system clock
Table 2-5 Signal Functions (Continued)
Freescale Semiconductor, Inc.
RXD1, RXD2
TXD1, TXD2
For More Information On This Product,
Mnemonic
PCS[3:0]
PQA[7:0]
PQB[7:0]
IRQ[7:1]
TP[15:0]
IFETCH
MA[2:0]
SIZ[1:0]
RESET
EPEB0
T2CLK
QUOT
MISO
MOSI
2-1.
RMC
SCK
R/W
TSC
XFC
SS
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SIGNAL DESCRIPTIONS
Rev. 25 June 03
Indicates instruction pipeline activity
Provides an interrupt priority level to the CPU
When external multiplexing is used, these pins provide the ad-
dresses to the external multiplexer
Serial input to QSPI in master mode;
serial output from QSPI in slave mode
Serial output from QSPI in master mode;
serial input to QSPI in slave mode
QSPI Peripheral Chip Select
QADC64 port A analog inputs and I/O port PQA[7:0]
QADC64 port B analog inputs and input-only port PQB[7:0]
Provides the quotient bit of the polynomial divider (test mode only)
Indicates the direction of data transfer on the bus
System reset
Indicates an indivisible read-modify-write instruction
Serial input to the SCI
Clock output from QSPI in master mode; clock input from QSPI in
slave mode
Indicates the number of bytes remaining to be transferred during a
bus cycle
Causes serial transmission when QSPI is in slave mode; chip-se-
lect in master mode
TPU3 clock input
Bidirectional TPU3 channels
Places all output drivers in a high impedance state
Serial output from the SCI
When asserted, allows CMFI block 0 to be programmed or erased.
Connection for external phase-locked loop filter capacitor
Function
Figure
2-1. Note that
MOTOROLA
2-7