MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 375

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

10.2 CMFI EEPROM Interface
MC68F375
REFERENCE MANUAL
The IMB3 provides a flexible, high performance bus capable of supporting a family of
parts.
Initialize program/erase sequence — The write to the high voltage control register
that changes the SES bit from a 0 to a 1.
Master reset — The hardware reset that resets the entire CMFI.
MoneT — The CMFI EEPROM’s FLASH bit cell.
Over programmed — By exceeding the specified programming time and/or voltage,
a CMFI bit may be over programmed. This bit causes erased bits in the same column
on the same array block to read as programmed.
Programming write — A word write to a CMFI array address to transfer information
into a program page buffer. The CMFI EEPROM accepts programming writes after ini-
tializing the program sequence until the EHV bit is changed from a 0 to a 1.
Program margin read — Special burst buffer updates of the CMFI array where the
CMFI EEPROM hardware adjusts the reference of the sense amplifier to check for cor-
rect program operation. All CMFI burst buffer updates between the first programming
write and clearing the SES bit are program margin reads.
Program page buffer — 64 bytes of information used to program the CMFI array. This
information is aligned to a 64-byte boundary within the CMFI array. Each CMFI module
has 1 program page buffer per block.
Read burst buffer — 32-byte block of information that is read from the CMFI array.
This information is aligned to a 32-byte boundary within the CMFI array. Each CMFI
module has two non-sequential burst buffers.
Reserved registers — A location within the control register block which may have one
or more bits that are reserved for use by Motorola. These bits are not available for nor-
mal use.
Shadow information — An extra row (256 bytes) of the CMFI array used to provide
reset configuration information. This row may be accessed by setting the SIE bit in the
module configuration register and accessing the CMFI array, see
EEPROM Configuration Register
the lowest array block of the CMFI array.
System reset — A reset generated under software control that clears the high voltage
enable (EHV) bit of the CMFICTL register and forces the BIU into a state ready to
receive a new IMB3 access.
The CMFI module contains a slave BIU to the IMB3. The BIU controls access and
operation of the array through standard IMB3 reads and writes of the array and register
blocks in the CMFI module. Additionally, the CMFI uses external signals to provide
control and power to the module. These other external signals include an optional sig-
Freescale Semiconductor, Inc.
CDR MoneT FLASH FOR THE IMB3 (CMFI)
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
(CMFIMCR). The shadow information is always in
10.4.3 CMFI
MOTOROLA
10-5