MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 453

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

13.5.2.3 Input Period Measurement (IPM) Mode
MC68F375
REFERENCE MANUAL
If a 32-bit coherent operation is in progress when the falling edge is detected, the
transfer from B1 to B2 is deferred until the coherent operation is completed. Operation
of the DASM then continues on channels B and A as previously described.
The input pulse width is calculated by subtracting the value in data register B from the
value in data register A.
Figure 13-7
measurement.
IPM mode is selected by making MODE[3:0] = 0010.
This mode allows the period of an input signal to be determined by capturing two con-
secutive rising edges or two consecutive falling edges; successive input captures are
done on consecutive edges of the same polarity. The edge polarity is defined by the
EDPOL bit in the DASMSIC register.
This mode also allows the software to determine the logic level on the input pin at any
time by reading the IN bit in the DASMSIC register.
When the first edge having the selected polarity is detected, the time base bus value
is latched into the 16-bit data register A, the data in register B1 is transferred to data
register B2 and finally the data in register A is transferred to register B1. On this first
capture the FLAG bit is not set. On the second and subsequent captures, the FLAG
bit is set immediately before the data in register A is transferred to register B1.
When the second edge of the same polarity is detected, the time base bus value is
latched into data register A, the data in register B1 is transferred to data register B2,
the FLAG bit is set to signify that the beginning and end points of a complete period
have been captured, and finally data register A is transferred to register B1. This
DASMA captured value
B1 captured value
Notes:
Time base bus
Input signal
Figure 13-7 Input Pulse Width Measurement Example
provides an example of how the DASM can be used for input pulse width
B2 value
Mode selection; EDPOL = 1
FLAG bit
1. These values are accessible to the software.
2. These values are internal and are not accessible.
1
2
1
Freescale Semiconductor, Inc.
0x0500
For More Information On This Product,
0xxxxx
0xxxxx
0xxxxx
CONFIGURABLE TIMER MODULE (CTM9)
Go to: www.freescale.com
0x1000
0x1000
0xxxxx
0xxxxx
B
Rev. 25 June 03
0x1100
0x1100
0x1000
0x1000
A
FLAG reset
by software
0x1250
0x1250
0x1000
0x1100
B
0x1525
0x1525
0x1250
0x1250
A
FLAG reset
by software
0x16A0
0x1525
0x16A0
0x1250
B
MOTOROLA
13-27