MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 422

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

ROMBS3 — ROM Bootstrap Word 3
12.6 Operation
12.6.1 RESET Operation
MC68F375
REFERENCE MANUAL
MSB
NOTES:
15
U
RESET:
1
1. The default state of these bits is defined by customer-specified options.
The ROM module is accessed via the IMB3 by a bus master. It can be used to contain
either program information only or both data and program information. On master
reset, it can operate as a bootstrap ROM to provide CPU internal initialization informa-
tion during the CPU’s reset sequence or can be configured to never respond to the
bootstrap addresses.
The ROM uses master RESET to initialize all register bits to their reset values. The
LOCK bit will also be cleared if it’s default reset state is 0. During master reset, the
ROM BIU will monitor three inputs to the module (STOPIN, EMULIN, and EMULEN)
to determine if it should respond normally after reset or disable itself for testing pur-
poses, and if emulation mode is enabled.
The value of STOPIN is determined by the state of D[14] during master reset. If the
state of STOPIN is 1, the STOP bit in the ROMMCR register will be cleared to 0 and
the array will respond normally to the bootstrap address range and the ROM array
base address. If STOPIN is 0, the STOP bit will be set and the ROM array will be dis-
abled until the STOP bit is cleared either by an IMB3 write or until the next master reset
which occurs with STOPIN = 1. It will not respond to the bootstrap address range or
the ROM array base address in BAR (ROMBAH and ROMBAL), allowing an external
device to respond to the ROM array’s address space, and/or provide bootstrap infor-
mation. This allows the ROM to be disabled from outside of the device if necessary.
The value of EMULIN is determined by the state of D[10] and the value of EMULEN is
determined by the state of D[13] during master reset. If the state of either EMULIN or
EMULEN is 1, the EMUL bit in the ROMMCR register will be cleared to 0, ROM emu-
lation mode will not be enabled, and the array will respond normally to valid accesses.
If EMULIN and EMULEN are both 0, the EMUL bit in ROMMCR will be set and ROM
emulation mode will be enabled until the EMUL bit is cleared by either an IMB3 write
or the next master reset occurs with either EMULIN or EMULEN =1.
STOPIN, EMULIN and EMULEN are forced to the value of external pins during master
reset. These pins may be data pins for devices that have an external data bus, in which
case STOPIN, EMULIN and EMULEN will be driven by corresponding IMB3 lines. This
function is performed by the SCIM2E.
U
14
1
13
U
1
12
U
1
Freescale Semiconductor, Inc.
U
11
1
For More Information On This Product,
10
U
1
Go to: www.freescale.com
MASK ROM MODULE
U
9
1
Rev. 25 June 03
U
8
PC[15:0]
1
U
7
1
U
6
1
U
5
1
U
4
1
U
3
1
U
2
1
0xYF F836
MOTOROLA
U
1
1
LSB
12-8
U
0
1