MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 202

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
(FROM CONTROL REGISTER 0):
PRESCALER RATE SELECTION
SYSTEM CLOCK (FSYS)
To accommodate wide variations of the main MCU clock frequency (IMB system clock
– F
tem clock to a frequency within the specified QCLK tolerance range. To allow the A/D
conversion time to be maximized across the spectrum of system clock frequencies, the
QADC64 prescaler permits the frequency of QCLK to be software selectable. It also
allows the duty cycle of the QCLK waveform to be programmable.
The software establishes the basic high phase of the QCLK waveform with the PSH
(prescaler clock high time) field in QACR0, and selects the basic low phase of QCLK
with the PSL (prescaler clock low time) field. The combination of the PSH and PSL
parameters establishes the frequency of the QCLK.
Queue 1 & 2 TIMER MODE RATE SELECTION
HIGH TIME CYCLES (PSH)
LOW TIME CYCLES (PSL)
ADD HALF CYCLE TO HIGH (PSA)
SYS
INPUT SAMPLE TIME (FROM CCW)
), QCLK is generated by a programmable prescaler which divides the MCU sys-
Figure 5-8 QADC64 Clock Subsystem Functions
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
5
DOWN COUNTER
Freescale Semiconductor, Inc.
8
For More Information On This Product,
ONE’S COMPLEMENT
5-BIT
COMPARE
2
3
DETECT
ZERO
5
3
Go to: www.freescale.com
2
7
Rev. 25 June 03
2
LOAD PSH
8
2
9
2
PERIODIC/INTERVAL
10
BINARY COUNTER
A/D CONVERTER
STATE MACHINE
TIMER SELECT
2
11
2
12
2
13
2
RESET QCLK
14
SET QCLK
2
15
2
16
2
17
( Fsys / ÷2 TO Fsys/÷40 )
GENERATE
QADC64 CLOCK
CLOCK
10
2
SAR CONTROL
SAR
PERIODIC/INTERVAL
TRIGGER EVENT
FOR Q1 AND Q2
QCLK
MOTOROLA
5-26