MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 424

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

12.6.5 Emulation Mode Operation
MC68F375
REFERENCE MANUAL
Write operations are only allowed to the control block. Write accesses to the array will
be ignored (IAACKB will not be asserted) unless the ROM is in emulation mode and
the device is in FREEZE mode.
read/write operation in emulation mode.)
The ROM module has a special emulation mode which allows external emulation of
the ROM array, with the module itself performing address decode and bus cycle ter-
mination for the external memory which replaces the array. Bootstrap operation is not
affected by emulation mode, nor is it emulated.
STOP affects array operation in emulation mode, the same way it does in normal oper-
ation. Accesses to the ROM module control registers are unaffected by emulation
mode.
Emulation mode is enabled by the EMUL bit in ROMMCR. EMUL can be written via
the IMB3 if STOP = 1, and it’s reset state is controlled by the state of the EMULIN and
EMULEN inputs to the module during master reset. EMULIN and EMULEN are driven
from external pins during RESET. If both EMULIN and EMULEN are low during reset,
the EMUL bit will be set in ROMMCR and ROM emulation mode will be enabled. If
either input is high during reset, EMUL is cleared and ROM emulation mode is
disabled.
EMULIN should be connected to a signal which is used to select whether or not the
ROM module should be placed in emulation mode, along with the external bus inter-
face. EMULEN should be connected to the same signal used to enable emulation
mode for the external bus interface. In this way, the ROM module cannot be placed in
emulation mode, unless the external bus interface is also in emulation mode. It also
allows the external bus interface to be placed in emulation without placing the ROM
module in emulation mode.
In emulation mode, the ROM will assert the ICSMB line on the IMB3 whenever an
access is made to a valid ROM array location, instead of asserting IAACKB. Valid
array access corresponds to an array location within the address range indicated by
the value in the ROMBAH and ROMBAL registers, and FC[2:0] indicate address space
requirements specified in ASPC[1:0] field of the ROMMCR register. The ROM will
assert ICSMB on all read accesses and will also assert ICSMB on write accesses if
the IFREEZE line on the IMB3 is asserted. The ROM will not assert the IAACKB line
if it asserts ICSMB. In response to ICSMB, the external bus interface of the device will
assert CSM on the SCIM2E, indicating an emulation mode access to the array, and
will run an special external bus cycle which will be terminated by the internal signal
IDTACKB instead of DSACKx. The ROM module will assert IDTACKB to terminate the
To emulate bootstrap operation, the emulation system should moni-
tor another chip select which is programmed to assert CSBOOT on
the SCIM2E, or the emulation system must monitor the external bus
to determine when a bootstrap vector is being requested by the CPU.
Freescale Semiconductor, Inc.
For More Information On This Product,
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MASK ROM MODULE
12.6.5 Emulation Mode Operation
Rev. 25 June 03
NOTE
describes array
MOTOROLA
12-10