MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 157

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.9.1 Chip-Select Pin Assignment Register
MC68F375
REFERENCE MANUAL
Chip-select assertion can be synchronized with bus control signals to provide output
enable, read/write strobe, or interrupt acknowledge signals. Chip-select logic can also
generate DSACK and AVEC signals internally. Each signal can also be synchronized
with the ECLK signal available on ADDR23.
When a memory access occurs, chip-select logic compares address space type,
address, type of access, transfer size, and interrupt priority (in the case of interrupt
acknowledge) to parameters stored in chip-select registers. If all parameters match,
the appropriate chip-select signal is asserted. Chip-select signals are active low. If a
chip-select function is given the same address as a microcontroller module or an inter-
nal memory array, an access to that address goes to the module or array, and the chip-
select signal is not asserted. The external address and data buses do not reflect the
internal access.
All chip-select signals except CSBOOT are disabled after the release of RESET, and
cannot be asserted until the R/W[1:0] and BYTE[1:0] fields in the corresponding option
register are programmed to non-zero values. CSBOOT is automatically enabled out of
reset in 8-bit and 16-bit expanded modes. Alternate functions for chip-select pins are
enabled if appropriate data bus pins are held low at the release of RESET. Refer to
4.7.8.2 Data Bus Mode Selection
diagram of a single chip-select circuit.
The pin assignment registers contain twelve 2-bit fields that determine the functions of
the chip-select pins. Each pin has two or three possible functions, as shown in
4-31
and
DSACK
BUS CONTROL
AVEC
Table
ADDRESS
INTERNAL
SIGNALS
Figure 4-22 Chip-Select Circuit Block Diagram
4-32.
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
GENERATOR
For More Information On This Product,
AVEC
BASE ADDRESS REGISTER
ADDRESS COMPARATOR
OPTION COMPARE
OPTION REGISTER
Go to: www.freescale.com
GENERATOR
Rev. 25 June 03
DSACK
for more information.
ASSIGNMENT
REGISTER
PIN
CONTROL
TIMING
AND
Figure 4-22
REGISTER
DATA
PIN
CHIP SEL BLOCK
PIN
is a functional
MOTOROLA
Table
4-75