MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 167

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.9.4.2 Chip-Select Reset Operation
MC68F375
REFERENCE MANUAL
Chip-select address match logic functions only after the SCIM2E has won arbitration,
and the resulting IACK cycle is transferred to the external bus. For this reason, inter-
rupt requests from modules other than the SCIM2E will never have their IACK cycles
terminated by chip-select generated AVEC or DSACK.
Use the procedure that follows to configure a chip select to provide IACK cycle termi-
nation.
If an interrupting device does not provide a vector number, an autovector must be gen-
erated, either by asserting the AVEC pin or by having the chip select assert AVEC
internally. The latter is accomplished by setting the chip-select option register AVEC
bit. This terminates the bus cycle.
The LSB of each of the 2-bit pin assignment fields in CSPAR0 and CSPAR1 has a
reset value of one. The reset values of the MSBs of each field are determined by the
states of DATA[7:1] during reset. Weak internal pull-up devices condition each of the
data lines so that chip-select operation is selected by default out of reset. Excessive
bus loading can overcome the internal pull-up devices, resulting in inadvertent config-
uration out of reset. Use external pull-up resistors or active devices to avoid this.
The base address fields in chip-select base address registers CSBAR[0,3, 5:10],
CSBAR3, and CSBAR0 and chip-select option registers CSOR[10:5], CSOR3, and
CSOR0 have the reset values shown in
option register have a reset value of “disable”, so that a chip-select signal cannot be
asserted until the base and option registers are initialized.
1. Program the base address field to all ones.
2. Program block size to no more than 64 Kbytes, so that the address comparator
3. Set the R/W field to read only. An interrupt acknowledge cycle is performed as
4. Set the BYTE field to lower byte when using a 16-bit port, as the external vector
checks ADDR[19:16] against the corresponding bits in the base address regis-
ter. (The CPU space bus cycle type is placed on ADDR[19:16]).
a read in CPU space.
for a 16-bit port is fetched from the lower byte. Set the BYTE field to upper byte
when using an 8-bit port.
ACKNOWLEDGE
Figure 4-23 CPU Space Encoding for Interrupt Acknowledge
INTERRUPT
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
FUNCTION
1 1 1
2
CODE
For More Information On This Product,
0
23
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Go to: www.freescale.com
CPU SPACE
TYPE FIELD
Rev. 25 June 03
19
Table
16
ADDRESS BUS
4-40. The BYTE and R/W fields of each
LEVEL
CPU SPACE IACK TIM
0
1
MOTOROLA
4-85