MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 421

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

12.5 Bootstrap Information Words (ROMBS0–ROMBS3)
ROMBS0 — ROM Bootstrap Word 0
ROMBS1 — ROM Bootstrap Word 1
ROMBS2 — ROM Bootstrap Word 2
MC68F375
REFERENCE MANUAL
Bit(s)
MSB
MSB
MSB
NOTES:
NOTES:
NOTES:
15:0
31
U
15
U
31
U
RESET:
RESET:
RESET:
1
1
1
Typically, reset vectors for the system CPU are contained in non-volatile memory and
are only fetched when the CPU comes out of reset. The bootstrap information for the
processor controlling the system are contained in the ROM module in the four words
ROMBS0–ROMBS3. ROMBS0 responds to address 0x000000, ROMBS1 responds to
0x000002, ROMBS2 to 0x000004 and ROMBS3 to 0x000006 on the IMB3. The boot-
strap information is specified by the user along with the contents of the array and is
programmed along with the contents of the array, on the same mask layer. These reg-
isters are read only from the IMB3 in normal mode or bootstrap mode. IMB3 writes do
not affect the contents of these registers. In bootstrap mode, ROMBS0–ROMBS3 only
respond to supervisor program space accesses. In normal mode, they only respond to
supervisor data space accesses.
1. The default state of these bits is defined by customer-specified options.
1. The default state of these bits is defined by customer-specified options.
1. The default state of these bits is defined by customer-specified options.
U
U
U
30
14
30
RSP[15:0]
1
1
1
Name
29
U
13
U
29
U
1
1
1
ROM signature pattern. These 16 bits, when concatenated with the 3 bits contained in SIGHI,
form a 19-bit unique signature used to verify the contents of the ROM array. This information is
programmed along with the contents of the array, on the same mask layer.
28
U
12
U
28
U
1
1
1
Freescale Semiconductor, Inc.
U
U
U
27
11
27
1
1
1
For More Information On This Product,
Table 12-5 SIGLO Bit Settings
26
U
10
U
26
U
1
1
1
Go to: www.freescale.com
MASK ROM MODULE
25
U
U
25
U
9
1
1
1
Rev. 25 June 03
U
U
U
24
24
SP[31:16]
PC[31:16]
8
SP[15:0]
1
1
1
U
U
U
23
23
7
1
1
1
Description
22
U
U
22
U
6
1
1
1
21
U
U
21
U
5
1
1
1
U
U
U
20
20
4
1
1
1
19
U
U
19
U
3
1
1
1
18
U
U
18
U
2
1
1
1
0xYF F830
0xYF F832
0xYF F834
MOTOROLA
U
U
U
17
17
1
1
1
1
LSB
LSB
LSB
12-7
U
U
U
16
16
0
1
1
1