MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 292

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

QSCI1SR — QSCI1 Status Register
6.9.2.2 QSCI1 Status Register
MC68F375
REFERENCE MANUAL
RESET:
Bit(s)
MSB
3:0
15
9
8
7
6
5
4
0
RESERVED
14
QTHEI
QBHEI
QTWE
0
Name
QTSZ
QRE
QTE
—
13
0
Transmitter queue top-half empty interrupt. When set, QTHEI enables an SCI1 interrupt when-
ever the QTHE flag in QSCI1SR is set. The interrupt is blocked by negating QTHEI. This bit refers
to the queue locations SCTQ[0:7].
0 = QTHE interrupt inhibited
1 = Queue top-half empty (QTHE) interrupt enabled
Transmitter queue bottom-half empty interrupt. When set, QBHEI enables an SCI1 interrupt
whenever the QBHE flag in QSCI1SR is set. The interrupt is blocked by negating QBHEI. This
bit refers to the queue locations SCTQ[8:15].
0 = QBHE interrupt inhibited
1 = Queue bottom-half empty (QBHE) interrupt enabled
Reserved
Queue transmit enable. When set, the transmit queue is enabled and the TDRE bit should be
ignored by software. The TC bit is redefined to indicate when the entire queue is finished trans-
mitting. When clear, the SCI1 functions as described in the previous sections and the bits related
to the queue (Section 5.5 and its subsections) should be ignored by software with the exception
of QTE.
0 = Transmit queue is disabled
1 = Transmit queue is enabled
Queue receive enable. When set, the receive queue is enabled and the RDRF bit should be
ignored by software. When clear, the SCI1 functions as described in the previous sections and
the bits related to the queue (Section 5.5 and its subsections) should be ignored by software with
the exception of QRE.
0 = Receive queue is disabled
1 = Receive queue is enabled
Queue transmit wrap enable. When set, the transmit queue is allowed to restart transmitting from
the top of the queue after reaching the bottom of the queue. After each wrap of the queue, QTWE
is cleared by hardware.
0 = Transmit queue wrap feature is disabled
1 = Transmit queue wrap feature is enabled
Queue transfer size. The QTSZ bits allow programming the number of data frames to be trans-
mitted. From 1 (QTSZ = 0b0000) to 16 (QTSZ = 0b1111) data frames can be specified. QTSZ is
loaded into QPEND initially or when a wrap occurs.
QOR
Table 6-31 QSCI1CR Bit Settings (Continued)
12
0
Freescale Semiconductor, Inc.
QTHF QBHF QTHE QBHE
QUEUED SERIAL MULTI-CHANNEL MODULE
11
For More Information On This Product,
1
10
1
Go to: www.freescale.com
9
1
Rev. 25 June 03
8
1
7
0
Description
6
0
QRPNT
5
0
4
0
3
0
2
0
0xYF FC2A
QPEND
MOTOROLA
1
0
LSB
6-58
0
0