MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 242

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

QIVR — QSMCM Interrupt Vector Register
QSPI_IL — Queued SPI Interrupt Level Register
6.6 QSMCM Pin Control Registers
MC68F375
REFERENCE MANUAL
Bit(s)
Bit(s)
Bit(s)
RESET:
RESET:
Table 6-7
7:3
2:0
7:0
7:3
2:0
7
0
7
0
ILQSPI[2:0]
ILSCI[2:0]
INTV[7:0]
Name
Name
Name
lists the three QSMCM pin control registers.
—
—
6
0
6
0
Reserved
Interrupt level of SCI. When an interrupt request is made,the ILSCI value determines
which of the interrupt request signals is asserted. When a request is acknowledged, the
QSMCM compares this value to a mask value supplied by the CPU32 to determine
whether to respond. The field must have a value in the range 0x0 (interrupts disabled) to
0x7 (highest priority). If ILQSPI[2:0] and ILSCI[2:0] have the same non-zero value, and
both submodules simultaneously request interrupt service, the QSPI has priority.
Interrupt vector number. The values of INTV[7:1] are the same for both QSPI and SCI
interrupt requests; the value of INTV0 used during an interrupt acknowledge cycle is sup-
plied by the QSMCM. INTV0 is at logic level zero during an SCI interrupt and at logic level
one during a QSPI interrupt. A write to INTV0 has no effect. Reads of INTV0 return a
value of one.
Reserved
Interrupt level of QSPI. When an interrupt request is made, the ILQSPI value determines
which of the interrupt request signals is asserted; when a request is acknowledged, the
QSMCM compares this value to a mask value supplied by the CPU32 to determine
whether to respond. ILQSPI must have a value in the range 0x0 (interrupts disabled) to
0x7 (highest priority).
Freescale Semiconductor, Inc.
RESERVED
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
5
0
5
0
Table 6-6 QSPI_IL Bit Settings
Table 6-5 QIVR Bit Settings
Table 6-4 QILR Bit Settings
Go to: www.freescale.com
Rev. 25 June 03
4
0
4
0
INTV[7:0]
3
1
3
0
Description
Description
Description
2
1
2
0
ILQSPI[2:0]
1
1
1
0
0xYF FC05
0xYF FC07
MOTOROLA
0
1
0
0
6-8