MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 284

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

6.8.6 SCI Pins
6.8.7 SCI Operation
6.8.7.1 Definition of Terms
MC68F375
REFERENCE MANUAL
Bit(s)
15:9
8:0
The RXD1 and RXD2 pins are the receive data pins for the SCI1 and SCI2, respec-
tively. TXD1 and TXD2 are the transmit data pins for the two SCI modules. An external
clock pin, ECK, is common to both SCIs. The pins and their functions are listed in
Table
The SCI can operate in polled or interrupt-driven mode. Status flags in SCxSR reflect
SCI conditions regardless of the operating mode chosen. The TIE, TCIE, RIE, and ILIE
bits in SCCxR1 enable interrupts for the conditions indicated by the TDRE, TC, RDRF,
and IDLE bits in SCxSR, respectively.
• Bit-time — The time required to transmit or receive one bit of data, which is equal
• Start bit — One bit-time of logic zero that indicates the beginning of a data frame.
• Stop bit— One bit-time of logic one that indicates the end of a data frame.
• Frame — A complete unit of serial information. The SCI can use 10-bit or 11-bit
• Data frame — A start bit, a specified number of data or information bits, and at
• Idle frame — A frame that consists of consecutive ones. An idle frame has no start
External Clock
Transmit Data
Receive Data
to one cycle of the baud frequency.
A start bit must begin with a one-to-zero transition and be preceded by at least
three receive time samples of logic one.
frames.
least one stop bit.
Pin Names
R[8:0]/
Name
T[8:0]
6-27.
—
Reserved
R[7:0]/T[7:0] contain either the eight data bits received when SCxDR is read, or the eight data
bits to be transmitted when SCxDR is written. R8/T8 are used when the SCI is configured for
nine-bit operation (M = 1). When the SCI is configured for 8-bit operation, R8/T8 have no mean-
ing or effect.
Accesses to the lower byte of SCxDR triggers the mechanism for clearing the status bits or for
initiating transmissions whether byte, half-word, or word accesses are used.
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
RXD1, RXD2
TXD1, TXD2
Mnemonic
Table 6-26 SCxSR Bit Settings
Table 6-27 SCI Pin Functions
ECK
Go to: www.freescale.com
Rev. 25 June 03
Receiver disabled
Receiver enabled
Transmitter disabled
Transmitter enabled
Receiver disabled
Receiver enabled
Transmitter disabled
Transmitter enabled
Mode
Description
General purpose input
Serial data input to SCI
General purpose output
Serial data output from SCI
Not used
Alternate input source to baud
Not used
Alternate input source to baud
Function
MOTOROLA
6-50