MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 344

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

8.3.3 Interchannel Communication
8.3.4 Programmable Channel Service Priority
8.3.5 Coherency
8.3.6 Emulation Support
MC68F375
REFERENCE MANUAL
ation, so that any channel can be configured to perform any time function. Any function
can operate on the calling channel, and, under program control, on another channel
determined by the program or by a parameter. The user controls the combination of
time functions.
The autonomy of the TPU3 is enhanced by the ability of a channel to affect the oper-
ation of one or more other channels without CPU intervention. Interchannel
communication can be accomplished by issuing a link service request to another chan-
nel, by controlling another channel directly, or by accessing the parameter RAM of
another channel.
The TPU3 provides a programmable service priority level to each channel. Three pri-
ority levels are available. When more than one channel of a given priority requests
service at the same time, arbitration is accomplished according to channel number. To
prevent a single high-priority channel from permanently blocking other functions, other
service requests of the same priority are performed in channel order after the lowest-
numbered, highest-priority channel is serviced.
For data to be coherent, all available portions of the data must be identical in age, or
must be logically related. As an example, consider a 32-bit counter value that is read
and written as two 16-bit words. The 32-bit value is read-coherent only if both 16-bit
portions are updated at the same time, and write-coherent only if both portions take
effect at the same time. Parameter RAM hardware supports coherent access of two
adjacent 16-bit parameters. The host CPU must use a long-word operation to guaran-
tee coherency.
Although factory-programmed time functions can perform a wide variety of control
tasks, they may not be ideal for all applications. The TPU3 provides emulation capa-
bility that allows the user to develop new time functions. Emulation mode is entered by
setting the EMU bit in TPUMCR. In emulation mode, an auxiliary bus connection is
made between the DPTRAM and the TPU3, and access to DPTRAM via the intermod-
ule bus is disabled. A 9-bit address bus, a 32-bit data bus, and control lines transfer
information between the modules. To ensure exact emulation, DPTFLASH module
access timing remains consistent with access timing of the TPU microcode ROM con-
trol store.
To support changing TPU application requirements, Motorola has established a TPU
function library. The function library is a collection of TPU functions written for easy
assembly in combination with each other or with custom functions. Refer to Motorola
Programming Note TPUPN00/D,
tion Mode
for information about developing custom functions and accessing the TPU
Freescale Semiconductor, Inc.
For More Information On This Product,
TIME PROCESSOR UNIT 3
Go to: www.freescale.com
Using the TPU Function Library and TPU Emula-
Rev. 25 June 03
MOTOROLA
8-4