MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 343

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

8.2.5 Host Interface
8.2.6 Parameter RAM
8.3 TPU Operation
8.3.1 Event Timing
8.3.2 Channel Orthogonality
MC68F375
REFERENCE MANUAL
The host interface registers allow communication between the CPU and the TPU3,
both before and during execution of a time function. The registers are accessible from
the IMB through the TPU3 bus interface unit. Refer to
register bit/field definitions and address mapping.
Parameter RAM occupies 256 bytes at the top of the system address map. Channel
parameters are organized as 128 16-bit words. Channels zero through 15 each have
eight parameters. The parameter RAM address map in
shows how parameter words are organized in memory.
The CPU specifies function parameters by writing to the appropriate RAM address.
The TPU3 reads the RAM to determine channel operation. The TPU3 can also store
information to be read by the CPU in the parameter RAM. Detailed descriptions of the
parameters required by each time function are beyond the scope of this manual. Refer
to the TPU Reference Manual (TPURM/AD) and the Motorola TPU Literature Package
(TPULITPAK/D) for more information.
All TPU3 functions are related to one of the two 16-bit time bases. Functions are syn-
thesized by combining sequences of match events and capture events. Because the
primitives are implemented in hardware, the TPU3 can determine precisely when a
match or capture event occurs, and respond rapidly. An event register for each chan-
nel provides for simultaneous match/capture event occurrences on all channels.
When a match or input capture event requiring service occurs, the affected channel
generates a service request to the scheduler. The scheduler determines the priority of
the request and assigns the channel to the microengine at the first available time. The
microengine performs the function defined by the content of the control store or emu-
lation RAM, using parameters from the parameter RAM.
Match and capture events are handled by independent channel hardware. This pro-
vides an event accuracy of one time-base clock period, regardless of the number of
channels that are active. An event normally causes a channel to request service. The
time needed to respond to and service an event is determined by which channels and
the number of channels requesting service, the relative priorities of the channels
requesting service, and the microcode execution time of the active functions. Worst-
case event service time (latency) determines TPU3 performance in a given applica-
tion. Latency can be closely estimated. For more information, refer to the TPU
Reference Manual (TPURM/AD).
Most timer systems are limited by the fixed number of functions assigned to each pin.
All TPU3 channels contain identical hardware and are functionally equivalent in oper-
Freescale Semiconductor, Inc.
For More Information On This Product,
TIME PROCESSOR UNIT 3
Go to: www.freescale.com
Rev. 25 June 03
8.4.18 TPU3 Parameter RAM
8.4 Programming Model
MOTOROLA
8-3
for