MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 268

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

6.7.5.1 Clock Phase and Polarity
6.7.5.2 Baud Rate Selection
MC68F375
REFERENCE MANUAL
QSPI operation is initiated by setting the SPE bit in SPCR1. Shortly after SPE is set,
the QSPI executes the command at the command RAM address pointed to by
NEWQP. Data at the pointer address in transmit RAM is loaded into the data serializer
and transmitted. Data that is simultaneously received is stored at the pointer address
in receive RAM.
When the proper number of bits have been transferred, the QSPI stores the working
queue pointer value in CPTQP, increments the working queue pointer, and loads the
next data for transfer from transmit RAM. The command pointed to by the incremented
working queue pointer is executed next, unless a new value has been written to
NEWQP. If a new queue pointer value is written while a transfer is in progress, that
transfer is completed normally.
When the CONT bit in a command RAM byte is set, PCS pins are continuously driven
to specified states during and between transfers. If the chip-select pattern changes
during or between transfers, the original pattern is driven until execution of the follow-
ing transfer begins. When CONT is cleared, the data in register PORTQS is driven
between transfers. The data in PORTQS must match the inactive states of SCK and
any peripheral chip-selects used.
When the QSPI reaches the end of the queue, it sets the SPIF flag. If the SPIFIE bit
in SPCR2 is set, an interrupt request is generated when SPIF is asserted. At this point,
the QSPI clears SPE and stops unless wraparound mode is enabled.
In master mode, data transfer is synchronized with the internally-generated serial
clock SCK. Control bits, CPHA and CPOL, in SPCR0, control clock phase and polarity.
Combinations of CPHA and CPOL determine upon which SCK edge to drive outgoing
data from the MOSI pin and to latch incoming data from the MISO pin.
Baud rate is selected by writing a value from two to 255 into the SPBR field in SPCR0.
The QSPI uses a modulus counter to derive the SCK baud rate from the MCU system
clock.
The following expressions apply to the SCK baud rate:
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
SCK Baud Rate =
SPBR =
Go to: www.freescale.com
Rev. 25 June 03
2 x SCK Baud Rate Desired
or
2 x SPBR
f
SYS
f
SYS
MOTOROLA
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