MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 283

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

6.8.5 SCI Data Register (SCxDR)
SCxDR — SCI Data Register
MC68F375
REFERENCE MANUAL
RESET:
Bit(s)
MSB
15
2
1
0
0
The SCxDR consists of two data registers located at the same address. The receive
data register (RDRx) is a read-only register that contains data received by the SCI
serial interface. Data is shifted into the receive serial shifter and is transferred to
RDRx. The transmit data register (TDRx) is a write-only register that contains data to
be transmitted. Data is first written to TDRx, then transferred to the transmit serial
shifter, where additional format bits are added before transmission.
14
0
Name
NF
FE
PF
13
0
RESERVED
Noise error flag. NF is set when the receiver detects noise on a valid start bit, on any of the data
bits, or on the stop bit(s). It is not set by noise on the idle line or on invalid start bits. Each bit is
sampled three times for noise. If the three samples are not at the same logic level, the majority
value is used for the received data value, and NF is set. NF is not set until the entire frame is
received and RDRF is set.
Although no interrupt is explicitly associated with NF, an interrupt can be generated with RDRF,
and the interrupt handler can check NF.
0 = No noise detected in the received data.
1 = Noise detected in the received data.
For receiver queue operation NF is cleared when SCxSR is read with NF set, followed by a read
Framing error. FE is set when the receiver detects a zero where a stop bit (one) was expected.
A framing error results when the frame boundaries in the received bit stream are not synchro-
nized with the receiver bit counter. FE is not set until the entire frame is received and RDRF is set.
Although no interrupt is explicitly associated with FE, an interrupt can be generated with RDRF,
and the interrupt handler can check FE.
0 = No framing error detected in the received data.
1 = Framing error or break detected in the received data.
Parity error. PF is set when the receiver detects a parity error. PF is not set until the entire frame
is received and RDRF is set.
Although no interrupt is explicitly associated with PF, an interrupt can be generated with RDRF,
and the interrupt handler can check PF.
0 = No parity error detected in the received data.
1 = Parity error detected in the received data.
12
0
of SCRQ[0:15].
Table 6-25 SCxSR Bit Settings (Continued)
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
11
For More Information On This Product,
0
10
0
Go to: www.freescale.com
9
0
Rev. 25 June 03
R8/T8 R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0
U
8
U
7
Description
U
6
U
5
0xYF FC0E, 0xYF FC26
U
4
U
3
U
2
MOTOROLA
U
1
LSB
6-49
U
0