MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 409

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

11.2.2 SRAM Array
11.2.2.1 SRAM Array Addressing
11.3 SRAM Module Control and Status Registers
11.3.1 Module Configuration Register (RAMMCR)
MC68F375
REFERENCE MANUAL
The SRAM array itself can be placed anywhere in the address map of the MCU by
means of the array base address registers. The high order address lines (IADDR[31:N]
N=13 and 9 for 8K and 512-byte arrays) are compared with the value in RAMBAH and
RAMBAL registers for a base address match. This value points to the lowest address
that SRAM data may be located and is always on a 8K or 512-byte boundary. The
SRAM array top is on a 256-byte boundary. The only restrictions on the base address
is that it must be on an address boundary greater than or equal to the array size. If the
SRAM array base address is located to overlap the SRAM control block then access
to the 8 bytes in the SRAM array located at the same address as the SRAM control
block are ignored allowing the control block to be accessed. Note this is only the 8
bytes in the SRAM control block; this mapping may have unknown results for other
modules.
The BIU of the SRAM module compares IADDR[31:N] (N = 13 for 8K and 9 for 512-
byte arrays) of the IMB3 with the value of the array base address registers. If they
match then the low address and ISIZ[1:0] are used to access the SRAM location in the
array. Addresses in the array that are not implemented will be ignored by the SRAM
module allowing an external device to respond to the address. Function codes are also
checked for the correct access rights. If the array is placed in supervisor space, user
accesses will be ignored allowing an external device to respond to the address. If the
array is placed in unrestricted space, it will respond to both user and supervisor
accesses. The array may also be placed in program space, or program/data space.
Program space allows the SRAM array to contain only program instructions for execu-
tion, or program counter relative addressing modes for operand fetches from the array.
Program/data space allows both program and data may be stored in the SRAM array.
The SRAM module control and status registers are used to control and monitor the
operation of the SRAM array. The following sections describe the operation of each
register in the SRAM control block. Since all the registers are in supervisor data space,
the only way to change the state of the registers is through a supervisor program. Any
other restrictions for making changes to the registers will be noted in the description of
the register. Unless otherwise noted, any source of master reset will cause register bits
to be forced to their reset state; while, system resets have no effect on the registers.
Reads to unimplemented bits will return “0”; while, writes have no effect.
All modules on the MCU contain a module configuration register. The RAMMCR reg-
ister bits configure the SRAM module for stop operation and for proper access rights
to the array.
Freescale Semiconductor, Inc.
STATIC RANDOM ACCESS MEMORY (SRAM)
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
MOTOROLA
11-3