MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 125

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.6.4.1 Breakpoint Acknowledge Cycle
MC68F375
REFERENCE MANUAL
Breakpoints stop program execution at a predefined point during system development.
Breakpoints can be used alone or in conjunction with background debug mode. On the
MC68F375 microcontroller, both hardware and software can initiate breakpoints.
The CPU32 BKPT instruction allows breakpoints to be inserted through software. The
CPU32 responds to this instruction by initiating a breakpoint acknowledge read cycle
in CPU space. It places the breakpoint acknowledge (0b0000) code on ADDR[19:16],
the breakpoint number (bits [2:0] of the BKPT opcode) on ADDR[4:2], and 0b0 (indi-
cating a software breakpoint) on ADDR1.
External breakpoint circuitry must decode the function code and address lines and
responds either by asserting BERR or placing an instruction word on the data bus and
asserting DSACK. If the bus cycle is terminated by DSACK, the CPU32 reads the
instruction on the data bus and inserts the instruction into the pipeline. (For 8-bit ports,
this instruction fetch may require two read cycles.)
If the bus cycle is terminated by BERR, the CPU32 performs illegal instruction excep-
tion processing. The CPU32 acquires the number of the illegal instruction exception
vector, computes the vector address from this number, loads the content of the vector
address into the PC, and jumps to the exception handler routine at that address.
Assertion of the BKPT input initiates a hardware breakpoint. The CPU32 responds by
initiating a breakpoint acknowledge read cycle in CPU space. The CPU32 places the
breakpoint acknowledge code of 0b0000 on ADDR[19:16], the breakpoint number
value of 0b111 on ADDR[4:2], and ADDR1 is set to 0b1, indicating a hardware
breakpoint.
STOP BROADCAST
ACKNOWLEDGE
ACKNOWLEDGE
BREAKPOINT
LOW POWER
INTERRUPT
Figure 4-13 CPU Space Address Encoding
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
FUNCTION
Freescale Semiconductor, Inc.
1 1 1
2
1 1 1
2
1 1 1
2
CODE
For More Information On This Product,
0
0
0
23
23
23
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Go to: www.freescale.com
ADDRESS BUS
Rev. 25 June 03
CPU SPACE
TYPE FIELD
19
19
19
CPU SPACE CYCLES
16
16
16
4
BKPT#
LEVEL
2
T 0
1
CPU SPACE CYC TIM
0
0
0
1
MOTOROLA
4-43