MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 354

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

8.4.5 TPU3 Interrupt Configuration Register
TICR — TPU3 Interrupt Configuration Register
8.4.6 Channel Interrupt Enable Register
CIER — Channel Interrupt Enable Register
MC68F375
REFERENCE MANUAL
CH 15 CH 14 CH 13 CH 12 CH 11 CH 10
Bit(s)
15:11
Bit(s)
MSB
MSB
10:8
15:0
15
15
7:4
3:0
0
RESET:
RESET:
The channel interrupt enable register (CIER) allows the CPU to enable or disable the
ability of individual TPU3 channels to request interrupt service. Setting the appropriate
bit in the register enables a channel to make an interrupt service request; clearing a
bit disables the interrupt.
14
14
0
CH[15:0]
Name
Name
RESERVED
CIBV
CIRL
—
—
13
13
0
Reserved
Channel interrupt request level. This three-bit field specifies the interrupt request level for all
channels. T field is used in conjunction with the ILBS field to determine the request level of TPU3
interrupts.
Channel interrupt base vector. The TPU is assigned 16 unique interrupt vector numbers, one
vector number for each channel. The CIBV field specifies the most significant nibble of all 16 TPU
channel interrupt vector numbers. The lower nibble of the TPU interrupt vector number is deter-
mined by the channel number on which the interrupt occurs.
Reserved.
Channel interrupt enable/disable
0 = Channel interrupts disabled
1 = Channel interrupts enabled
Note: The MSB (bit 0 in big-endian mode) represents CH15, and the LSB (bit 15 in big-endian
mode) represents CH0.
12
12
0
Freescale Semiconductor, Inc.
11
11
0
For More Information On This Product,
Table 8-10 CIER Bit Settings
Table 8-9 TICR Bit Settings
10
10
0
0
TIME PROCESSOR UNIT 3
Go to: www.freescale.com
CIRL
CH 9
9
0
9
0
Rev. 25 June 03
CH 8
8
0
8
0
CH 7
7
0
7
0
Description
Description
CH 6
6
0
6
0
CIBV
CH 5
5
0
5
0
CH 4
4
0
4
0
CH 3
3
3
0
CH 2
RESERVED
2
2
0
0xYF FE0A
0xYF FE08
MOTOROLA
CH 1
1
1
0
CH 0
LSB
LSB
8-14
0
0
0