MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 95

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.3.5 External Clock Mode
MC68F375
REFERENCE MANUAL
0=000
1=001
2=010
3=011
4=100
5=101
6=110
7=111
0=000
1=001
2=010
3=011
4=100
5=101
6=110
7=111
X=0
X=1
In external clock mode, the clock source, which should be 2x the desired system fre-
quency, must be driven onto the EXTAL pin. This clock is used to generate the system
clock directly (the VCO is turned off). At reset, the system clock frequency is one-half
the external clock frequency. If this frequency is the the maximum specified system
clock frequency, it must not violate strict minimum duty cycle requirements. A block
diagram of external clock mode is show in
In this mode, the six-stage Y divider and the one-stage X divider are placed in the clock
output path such that the input clock may be divided down by as much as 128 to pro-
duce the system clock. When this is done, it is not necessary to meet the input duty
cycle restrictions. The Y bit divider is a six-stage divider chain whose output tap is con-
trolled by the three Y register bits. The X bit divider is a single-stage divider which is
bypassed when X is set to 1. X is 1 and Y is 0 after reset, so that the system clock is
the same as the external clock.
Y
Y
Table 4-7 CLKOUT In Fast Reference Mode with 4.0 MHz Reference
2,000,000
1,000,000
4,000,000
2,000,000
1,000,000
500,000
250,000
125,000
500,000
250,000
125,000
W=000
W=000
62,500
31,250
31,250
62,500
62,500
Setting Y to 7 has the same effect as setting it to 6; the maximum divi-
sor is 2
Therefore, changing the X or Y bits in this mode causes the fre-
quency to change without a delay.
4,000,000
2,000,000
1,000,000
8,000,000 12,000,000 16,000,000 20,000,000 24,000,000 28,000,000 32,000,000
4,000,000
2,000,000
1,000,000
500,000
250,000
125,000
500,000
250,000
125,000
125,000
6
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
W=001
W=001
62,500
62,500
. The X and Y bit dividers are in the output clock path.
Freescale Semiconductor, Inc.
For More Information On This Product,
6,000,000
3,000,000
1,500,000
6,000,000
3,000,000
1,500,000
750,000
375,000
187,500
750,000
375,000
187,500
187,500
W=010
W=010
93,750
93,750
Go to: www.freescale.com
Rev. 25 June 03
8,000,000
4,000,000
2,000,000
1,000,000
8,000,000
4,000,000
2,000,000
1,000,000
500,000
250,000
125,000
125,000
500,000
250,000
250,000
W=011
W=011
NOTE
Figure
10,000,000 12,000,000 14,000,000 16,000,000
10,000,000 12,000,000 14,000,000 16,000,000
5,000,000
2,500,000
1,250,000
5,000,000
2,500,000
1,250,000
625,000
312,500
156,250
156,250
625,000
312,500
312,500
W=100
W=100
4-4.
6,000,000
3,000,000
1,500,000
6,000,000
3,000,000
1,500,000
750,000
375,000
187,500
187,500
750,000
375,000
375,000
W=101
W=101
7,000,000
3,500,000
1,750,000
7,000,000
3,500,000
1,750,000
875,000
437,500
218,750
218,750
375,000
187,500
187,500
W=110
W=110
MOTOROLA
8,000,000
4,000,000
2,000,000
1,000,000
8,000,000
4,000,000
2,000,000
1,000,000
500,000
250,000
250,000
500,000
500,000
W=111
W=111
4-13