MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 166

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.9.4 Chip-Select Operation
4.9.4.1 Using Chip-Select Signals for Interrupt Acknowledge Cycle Termination
MC68F375
REFERENCE MANUAL
the specified chip select will be asserted. This field only affects the response of chip-
select logic to IACK cycles and does not affect interrupt recognition by the CPU32.
Setting IPL[2:0] to 0b000 when SPACE[1:0] = 0b00 will cause chip-select assertion
regardless of the IACK cycle priority, provided other option register conditions are met.
When SPACE[1:0] = 0b01, 0b10, or 0b11, the IPL field specifies whether chip-select
assertion should occur during accesses to data space, program space, or both.
When the MCU makes an access, each enabled chip-select circuit compares the fol-
lowing items:
When a match occurs, the chip-select signal is asserted. Assertion occurs at the same
time as AS or DS assertion in asynchronous mode. Assertion is synchronized with
ECLK in synchronous mode. In asynchronous mode, the DSACK field specifies inter-
nal or external DSACK assertion and the number of wait states inserted if internal
DSACK assertion is selected.
The number of wait states needed by an external device is determined by its access
time. Normally, wait states are inserted into the bus cycle during state S3 until a
peripheral asserts DSACK. If a peripheral does not generate DSACK, internal DSACK
generation must be selected and a predetermined number of wait states can be pro-
grammed into the chip-select option register.
Ordinary bus cycles are issued in supervisor or user space. Interrupt acknowledge bus
cycles are issued in CPU space. Refer to
for more information. The SCIM2E chip selects operate identically in each type of
space, but base address and option registers must be properly programmed for each
type of external bus cycle.
During a CPU space cycle, bits [15:3] of the appropriate base register must be config-
ured to match ADDR[23:11], as the address is compared to an address generated by
the CPU.
Figure 4-23
drive 0b111, designating a CPU space access. ADDR[3:1] denote interrupt priority,
and the space type field (ADDR[19:16]) is set to 0b1111, the interrupt acknowledge
code. The rest of the address lines are set to one.
• Function code signals FC[2:0] to the SPACE field, and to the IP field if the SPACE
• Appropriate address bus bits to base address field.
• The R/W signal to the R/W field.
• ADDR0 and/or SIZ to the BYTE field (only chip selects configured for 16-bit op-
• Priority of the interrupt being acknowledged (ADDR[3:1]) to the IPL field when the
field is not programmed for CPU space.
eration).
access is an interrupt acknowledge cycle and the SPACE field is programmed for
CPU space.
shows CPU space encoding for an interrupt acknowledge cycle. FC[2:0]
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
4.6.4 CPU Space Cycles
and
4.8 Interrupts
MOTOROLA
4-84