MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 274

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

6.7.7 Slave Wraparound Mode
MC68F375
REFERENCE MANUAL
segment address, then increments the address and continues storing as described
above. Note that PCS0/SS does not necessarily have to be negated between
transfers.
Once the proper number of bits (designated by BITS) are transferred, the QSPI stores
the received data in the receive data segment, stores the internal working queue
pointer value in CPTQP, increments the internal working queue pointer, and loads the
new transmit data from the transmit data segment into the data serializer. The internal
working queue pointer address is used the next time PCS0/SS is asserted, unless the
CPU writes to the NEWQP first.
The DT and DSCK command control bits are not used in slave mode. As a slave, the
QSPI does not drive the clock line nor the chip-select lines and, therefore, does not
generate a delay.
In slave mode, the QSPI shifts out the data in the transmit data segment. The trans-
mit data is loaded into the data serializer (refer to
the PCS0/SS pin is pulled low the MISO pin becomes active and the serializer then
shifts the 16 bits of data out in sequence, most significant bit first, as clocked by the
incoming SCK signal. The QSPI uses CPHA and CPOL to determine which incoming
SCK edge the MOSI pin uses to latch incoming data, and which edge the MISO pin
uses to drive the data out.
The QSPI transmits and receives data until reaching the end of the queue (defined as
a match with the address in ENDQP), regardless of whether PCS0/SS remains
selected or is toggled between serial transfers. Receiving the proper number of bits
causes the received data to be stored. The QSPI always transmits as many bits as it
receives at each queue address, until the BITS value is reached or PCS0/SS is
negated.
When the QSPI reaches the end of the queue, it always sets the SPIF flag, whether
wraparound mode is enabled or disabled. An optional interrupt to the CPU is gen-
erated when SPIF is asserted. At this point, the QSPI clears SPE and stops unless
wraparound mode is enabled. A description of SPIFIE bit can be found in 4.3.3 QSPI
Control Register 2 (SPCR2).
In wraparound mode, the QSPI cycles through the queue continuously. Each time the
end of the queue is reached, the SPIF flag is set. If the CPU fails to clear SPIF, it
remains set, and the QSPI continues to send interrupt requests to the CPU (assuming
SPIFIE is set). The user may avoid causing CPU interrupts by clearing SPIFIE.
As SPIFIE is buffered, clearing it after the SPIF flag is asserted does not immediately
stop the CPU interrupts, but only prevents future interrupts from this source. To clear
the current interrupt, the CPU must read QSPI register SPSR with SPIF asserted, fol-
lowed by a write to SPSR with zero in SPIF (clear SPIF). Execution continues in
wraparound mode even while the QSPI is requesting interrupt service from the CPU.
The internal working queue pointer is incremented to the next address and the com-
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
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Rev. 25 June 03
Figure
6-1) for transmission. When
MOTOROLA
6-40