MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 26

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MC68F375BGMZP33

Manufacturer Part Number
MC68F375BGMZP33
Description
IC MPU 32BIT 33MHZ 217-PBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68F375BGMZP33

Processor Type
M683xx 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
217-PBGA
Processor Series
M683xx
Core
CPU32
Data Bus Width
32 bit
Program Memory Type
Flash
Program Memory Size
256 KB
Data Ram Size
10 KB
Interface Type
SPI, SCI, CAN
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
48
Number Of Timers
16
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
No

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68F375BGMZP33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Number
4-28 Reset Pin Function of CS[10:6] ......................................................................... 4-67
4-29 Reset Configuration for MC68F375 Memory Modules ...................................... 4-67
4-30 Partially (8-bit) Expanded Mode Reset Configuration........................................ 4-68
4-31 CSPAR0 Pin Assignments................................................................................. 4-76
4-32 CSPAR1 Pin Assignments................................................................................. 4-77
4-33 Reset Pin Function of CS[10:6] ......................................................................... 4-77
4-34 Pin Assignment Field Encoding ......................................................................... 4-77
4-35 Block Size Encoding .......................................................................................... 4-79
4-36 CSBARBT/CSBAR Bit Descriptions .................................................................. 4-80
4-37 CSOR Bit Descriptions ...................................................................................... 4-81
4-38 DSACK Field Encoding...................................................................................... 4-82
4-39 Interrupt Priority Level Field Encoding............................................................... 4-83
4-40 Chip-Select Base and Option Register
4-41 CSBOOT Base and Option Register
4-42 General-Purpose I/O Ports ................................................................................ 4-87
4-43 Port E Pin Assignments ..................................................................................... 4-90
4-44 Port F Pin Assignments ..................................................................................... 4-92
4-45 PFPAR Pin Functions ........................................................................................ 4-92
5-1 Multiplexed Analog Input Channels ....................................................................... 5-5
5-2 Analog Input Channels ........................................................................................ 5-11
5-3 Queue 1 Priority Assertion................................................................................... 5-15
5-4 QADC64 Clock Programmability ......................................................................... 5-28
5-5 QADC64 Status Flags and Interrupt Sources...................................................... 5-31
5-6 QADC64 Address Map ........................................................................................ 5-34
5-7 QADC64MCR Bit Settings .................................................................................. 5-35
5-8 QADC64INT Bit Settings .................................................................................... 5-36
5-9 PORTQA, PORTQB Bit Settings ........................................................................ 5-37
5-10 DDRQA Bit Settings.......................................................................................... 5-37
5-11 QACR0 Bit Settings .......................................................................................... 5-38
5-12 QACR1 Bit Settings .......................................................................................... 5-39
5-13 Queue 1 Operating Modes ................................................................................ 5-39
5-14 QACR2 Bit Settings .......................................................................................... 5-41
5-15 Queue 2 Operating Modes ................................................................................ 5-42
5-16 QASR0 Bit Settings .......................................................................................... 5-43
5-17 Queue Status..................................................................................................... 5-44
5-18 QASR1 Bit Settings .......................................................................................... 5-45
5-19 CCW Bit Settings .............................................................................................. 5-49
5-20 Non-Multiplexed Channel Assignments and Pin Designations.......................... 5-50
5-21 Multiplexed Channel Assignments and Pin Designations.................................. 5-50
5-22 AMUX I/O Functionality ..................................................................................... 5-53
6-1 QSMCM Register Map........................................................................................... 6-3
6-2 QSMCM Global Registers ..................................................................................... 6-5
MC68F375
REFERENCE MANUAL
Table
Reset Values ................................................................................................. 4-86
Reset Values ................................................................................................. 4-87
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
LIST OF TABLES
Rev. 25 June 03
MOTOROLA
Number
Page
xxvi

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