MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 66

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
MOVE to CCR
DIVSL/DIVUL
EORI to CCR
EORI to SR
Instruction
MOVE from
DIVS/DIVU
LPSTOP
ILLEGAL
MOVEA
MOVEA
CMPM
MOVE
CMPA
CMP2
EXTB
CMPI
DBcc
EORI
CMP
EOR
EXG
LINK
CCR
JMP
EXT
JSR
LEA
LSR
LSL
1
1
1
(An) , (An)
<ea>, Dr : Dq
<ea>, Dr : Dq
# <data>, SR
# <data>, Dn
#<data>, Dn
<ea>, <ea>
CCR, <ea>
<ea>, CCR
# <data>,
# <data>,
# <data>,
Operand
<ea>, Dn
<ea>, An
<ea>, Rn
<ea>, Dn
<ea>, Dq
Dn, <ea>
<ea>, An
<ea>, An
Dn, label
# <data>
USP, An
An, USP
Syntax
Rn, Rn
An, # d
Dn, Dn
Dn, Dn
<ea>
<ea>
<ea>
<ea>
<ea>
<ea>
CCR
none
Dn
Dn
Dn
Table 3-2 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc.
For More Information On This Product,
32/16
64/32
32/32
16, 32
32/32
Operand
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
16
8
8
16, 32
16, 32
none
none
none
Size
16
16
32
32
16
32
32
16
16
16
32
32
16
16
8
CENTRAL PROCESSOR UNIT
16
32
32
16 :
32 :
32 :
Go to: www.freescale.com
32
32
(Destination
(Destination
(Destination
(Destination
Lower bound
If condition false, then Dn
if Dn
Destination / Source
(signed or unsigned)
Destination / Source
(signed or unsigned)
Source
Data
Source
Source
Rn
Sign extended Destination
Sign extended Destination
SSP
SSP
SSP
Illegal instruction vector address
Destination
SP
<ea>
SP
Data
Source
Source
USP
An
CCR
Source
Rev. 25 June 03
4
4
USP
Rn
2
4
2
( 1), then PC
Destination
An
SR; interrupt mask
Destination
An
Destination
CCR
SR
SP; PC
SP, An
Destination
Destination
CCR
SSP; vector offset
SSP; PC
SSP; SR
0
Source), CCR shows results
Source), CCR shows results
Data), CCR shows results
Source), CCR shows results
PC
X/C
Rn
SR
CCR
(SP); SP
Upper bound, CCR shows result
(SP); destination
Destination
d
Destination
Destination
(SSP);
(SSP);
Destination
Description
1
PC
Destination
Destination
EBI; STOP
PC;
An, SP
(SSP);
PC
PC
d
SP
X/C
0
MOTOROLA
3-12