MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 270

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

6.7.5.5 Transfer Length
6.7.5.6 Peripheral Chip Selects
MC68F375
REFERENCE MANUAL
(DT = 0) or the specified delay period (DT = 1) is used. The following expression is
used to calculate the delay:
A zero value for DTL causes a delay-after-transfer value of 8192
quency (204.8 µs with a 40-MHz system clock).
If DT is zero in a command RAM byte, a standard delay is inserted.
Delay after transfer can be used to provide a peripheral deselect interval. A delay can
also be inserted between consecutive transfers to allow serial A/D converters to com-
plete conversion.
Adequate delay between transfers must be specified for long data streams because
the QSPI requires time to load a transmit RAM entry for transfer. Receiving devices
need at least the standard delay between successive transfers. If the system clock is
operating at a slower rate, the delay between transfers must be increased
proportionately.
There are two transfer length options. The user can choose a default value of eight
bits, or a programmed value from eight (0b1000) to 16 (0b0000) bits, inclusive.
Reserved values (from 0b0001 to 0b0111) default to eight bits. The programmed value
must be written into the BITS field in SPCR0. The BITSE bit in each command RAM
byte determines whether the default value (BITSE = 0) or the BITS value (BITSE = 1)
is used.
Peripheral chip-select signals are used to select an external device for serial data
transfer. Chip-select signals are asserted when a command in the queue is executed.
Signals are asserted at a logic level corresponding to the value of the PCS[3:0] bits in
each command byte. More than one chip-select signal can be asserted at a time, and
more than one external device can be connected to each PCS pin, provided proper
fanout is observed. PCS0 shares a pin with the slave select SS signal, which initiates
slave mode serial transfer. If SS is taken low when the QSPI is in master mode, a
mode fault occurs.
To configure a peripheral chip select, set the appropriate bit in PQSPAR, then config-
ure the chip-select pin as an output by setting the appropriate bit in DDRQS. The value
where DTL is in the range from one to 255.
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
Standard Delay after Transfer =
Delay after Transfer =
Go to: www.freescale.com
Rev. 25 June 03
32 x DTL
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SYS
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17
SYS
system clock fre-
MOTOROLA
6-36