MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 188

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

5.9.1 Conversion Cycle Times
MC68F375
REFERENCE MANUAL
VSSA
VDDA
PQA7
PQA0
PQB7
PQB0
VRH
VRL
Total conversion time is made up of initial sample time, final sample time, and resolu-
tion time. Initial sample time refers to the time during which the selected input channel
is driven by the buffer amplifier onto the sample capacitor. The buffer amplifier can be
disabled by means of the BYP bit in the CCW. During the final sampling period, ampli-
fier is bypassed, and the multiplexer input charges the RC DAC array directly. During
the resolution period, the voltage in the RC DAC array is converted to a digital value
and stored in the SAR.
Initial sample time is fixed at two QCLK cycles. Final sample time can be 2, 4, 8, or 16
QCLK cycles, depending on the value of the IST field in the CCW. Resolution time is
ten QCLK cycles.
Sample and resolution require a minimum of 14 QCLK clocks (7 s with a 2 MHz
QCLK). If the maximum final sample time period of 16 QCLKs is selected, the total
conversion time is 13.0 s with a 2 MHz QCLK.
Figure 5-5
sampling period of two QCLK cycles.
10-BIT A/D CONVERTER
ANALOG
POWER
illustrates the timing for conversions. This diagram assumes a final
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
10 BIT RC
D-C
Figure 5-4 QADC64 Module Block Diagram
Freescale Semiconductor, Inc.
COMPAR-
CHAN. DECODE & MUX
For More Information On This Product,
ATOR
SAMPLE
BUFFER
16: 1
INPUT
Go to: www.freescale.com
C
SAMP
Rev. 25 June 03
APPROXIMATION
6
SUCCESSIVE
STATE MACHINE & LOGIC
REGISTER
10
SAR Timing
BIAS CIRCUIT
CHAN.[5:0]
10
POWER
DOWN
2
SAR
CCW
BUF
BUF
10
10
STOP
RST
QCLK
WCCW
END OF CONV.
END OF SMP
CCW
SAR
QADC64 DETAIL BLOCK
MOTOROLA
RSAR
5-12