MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 160

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.9.1.1 Port C Data Register
PORTC — Port C Data Register
4.9.2 Chip-Select Base Address Registers
MC68F375
REFERENCE MANUAL
RESET:
From the release of reset, chip-select pin functions are determined by logic levels on
certain data bus pins. The data bus pins have weak internal pull-up devices but can
be held low by external logic. This allows a pin’s 16-bit chip-select function (data bus
pin(s) held high) or its alternate function (data bus pin(s) held low) to be selected at the
release of RESET. Refer to
The CSBOOT signal is enabled out of reset. The state of DATA0 during reset deter-
mines what port width CSBOOT uses. If DATA0 is held high, 16-bit port size is
selected. If DATA0 is held low, 8-bit port size is selected. In 8-bit expanded mode, the
state of DATA0 is ignored, and CSBOOT is configured for 8-bit operation.
A pin programmed as a discrete output will drive the value specified in the port C data
register. No discrete output function is available for the CSBOOT, CS0/BR, CSM/
BG,and CSE/BGACK pins. ADDR23 provides the ECLK output rather than a discrete
output signal.
When a pin is programmed for discrete output or alternate function, internal chip-select
logic still functions and can be used to generate DSACK or AVEC (to terminate IACK
cycles generated in response to external interrupt requests) internally on an address
and control signal match.
The port C data register (PORTC) latches data for port C pins programmed as discrete
outputs. When a pin is assigned as a discrete output, the value in this register appears
at the output. Port C bit 7 is not used. Writing to this bit has no effect, and it always
reads zero.
PORTC latches data for chip-select pins configured as discrete outputs.
Each chip select has an associated base address register, CSBAR[0], [3] and [5:10].
A base address is the lowest address in the block of addresses enabled by a chip
select. Block size is the extent of the address block above the base address. Block
size is determined by the value contained in BLKSZ[2:0]. Multiple chip selects
assigned to the same block of addresses must have the same number of wait states.
BLKSZ[2:0] determines which bits in the base address field are compared to corre-
sponding bits on the address bus during an access. Provided other constraints
determined by option register fields are also satisfied, when a match occurs, the asso-
ciated chip-select signal is asserted.
7
0
0
PC6
6
1
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
For More Information On This Product,
PC5
5
1
4.7.8.2 Data Bus Mode Selection
Go to: www.freescale.com
PC4
Rev. 25 June 03
4
1
Table 4-35
PC3
3
1
shows BLKSZ[2:0] encoding.
PC2
2
1
for more information.
PC1
1
1
0xYF FA41
MOTOROLA
LSB
PC0
0
1
4-78