MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 431

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

13.2.1 The FCSM Counter
MC68F375
REFERENCE MANUAL
16-bit counter. A software control register selects whether the clock input to the
counter is one of the taps from the prescaler or an input pin. The polarity of the external
input pin is also programmable. The free-running counter submodule operation is
comparable to the MC68HC11 counter.
A block diagram of the FCSM is shown in
FCSM are a 16-bit loadable free-running up-counter, a clock selector, a time base bus
driver and an interrupt interface.
The FCSM counter section comprises a 16-bit register and a 16-bit up-counter. Read-
ing the register transfers the contents of the counter to the data bus, while a write to
the register loads the counter with the new value. Overflow of the counter is defined to
be the transition from 0xFFFF to 0x0000. An overflow condition causes the COF flag
bit in the FCSMSIC register to be set.
Input pin
CTMC
In order to be able to count, the FCSM requires the CPSM clock sig-
nals to be present. On coming out of reset, the FCSM will not count
internal or external events until the prescaler in the CPSM starts run-
ning (when the software sets the PRUN bit). This allows all counters
in the CTM submodules to be synchronized.
Reset presets the counter register to 0x0000. Writing 0x0000 to the
counter register while the counter’s value is 0xFFFF does not set the
Submodule bus
6 clocks (PCLKx) from prescaler
Freescale Semiconductor, Inc.
For More Information On This Product,
detect
CONFIGURABLE TIMER MODULE (CTM9)
Edge
Figure 13-2 FCSM Block Diagram
TBBA
Go to: www.freescale.com
IN
Control register bits
TBBB
Rev. 25 June 03
CLK2
select
Clock
CLK1 CLK0
NOTE
NOTE
Figure
16-bit up counter
select
Bus
13-2. The main components of the
COF
Time base buses
Control register bits
DRVA DRVB
Control register bits
IL2
Overflow
IL1
IL1
IL0 IARB3
Interrupt
control
MOTOROLA
13-5