MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 131

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.6.5.3 Retry Operation
4.6.5.4 Halt Operation
MC68F375
REFERENCE MANUAL
Multiple bus errors within a single instruction that can generate multiple bus cycles
cause a single bus error exception after the instruction has been executed.
Immediately after assertion of a second BERR, the MCU halts and drives the HALT
line low. Only a reset can restart a halted MCU. However, bus arbitration can still
occur. Refer to
address error that occurs after exception processing has been completed (during the
execution of the exception handler routine, or later) does not cause a double bus fault.
The MCU continues to retry the same bus cycle as long as the external hardware
requests it.
When an external device asserts BERR and HALT during a bus cycle, the MCU enters
the retry sequence. A delayed retry can also occur. The MCU terminates the bus cycle,
places the AS and DS signals in their inactive state, and does not begin another bus
cycle until the BERR and HALT signals are negated by external logic. After a synchro-
nization delay, the MCU retries the previous cycle using the same address, function
codes, data (for a write), and control signals. The BERR signal should be negated
before S2 of the read cycle to ensure correct operation of the retried cycle.
If BR, BERR, and HALT are all asserted on the same cycle, the EBI will enter the rerun
sequence but first relinquishes the bus to an external master. Once the external mas-
ter returns the bus and negates BERR and HALT, the EBI runs the previous bus cycle.
This feature allows an external device to correct the problem that caused the bus error
and then try the bus cycle again.
The MCU retries any read or write cycle of an indivisible read-modify-write operation
separately. RMC remains asserted during the entire retry sequence. The MCU will not
relinquish the bus while RMC is asserted. Any device that requires the MCU to give up
the bus and retry a bus cycle during a read-modify-write cycle must assert BERR and
BR only (HALT must remain negated). The bus error handler software should examine
the read-modify-write bit in the special status word and take the appropriate action to
resolve this type of fault when it occurs. Refer to the
MRM/AD)
When HALT is asserted while BERR is not asserted, the MCU halts external bus activ-
ity after negation of DSACK. The MCU may complete the current word transfer in
progress. For a long-word to byte transfer, this could be after S2 or S4. For a word to
byte transfer, activity ceases after S2.
Negating and reasserting HALT according to timing requirements provides single-step
(bus cycle to bus cycle) operation. The HALT signal affects external bus cycles only,
so that a program that does not use the external bus can continue executing.
stack frame during a return from exception (RTE) instruction.
for additional information on read-modify-write and retry operations.
4.6.6 External Bus Arbitration
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
for more information. A bus error or
SCIM Reference Manual (SCI-
MOTOROLA
4-49