MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 134

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.7 Reset
4.7.1 SCIM2E Reset Control Logic
MC68F375
REFERENCE MANUAL
When show cycles are enabled, DS is asserted externally during internal cycles, and
internal data is driven out on the external data bus. Because internal cycles normally
continue to run when the external bus is granted, one SHEN[1:0] encoding halts inter-
nal bus activity while there is an external master.
The SIZ[1:0] signals reflect bus allocation during show cycles. Only the appropriate
portion of the data bus is valid during the cycle. During a byte write to an internal
address, the portion of the bus that represents the byte that is not written reflects inter-
nal bus conditions, and is indeterminate. During a byte write to an external address,
the data multiplexer in the SCIM2E drives the value of the byte that is written to both
halves of the data bus.
Reset occurs when an active low logic level on the RESET pin is clocked into the
SCIM2E. The RESET input is synchronized to the system clock. If there is no clock
when RESET is asserted, reset does not occur until the clock starts. Resets are
clocked to allow completion of write cycles in progress at the time RESET is asserted.
Reset procedures handle system initialization and recovery from catastrophic failure.
The MCU performs resets with a combination of hardware and software. The SCIM2E
determines whether a reset is valid, asserts control signals, performs basic system
configuration and boot memory selection based on hardware mode-select inputs, then
passes control to the CPU32.
The SCIM2E reset control logic differs somewhat from the SCIM. Do not use informa-
tion in SCIM documentation for the SCIM2E. As with the SCIM, the asserted state of
the external reset pin is ‘0’. The released state is ‘1’. The external circuit must make
some provision to pull the reset pin high (usually, just a pullup resistor and a capacitor
to ground) when the SCIM2’s reset controller releases reset. The specified maximum
time in which external circuit must release the reset pin (the input signal must be at or
above VIH) has been extended by approximately 180 clock cycles (22.5 s at eight
MHz for slow reference clock mode, 45 s at four MHz for fast reference clock mode,
for more information about clock modes, see
For the SCIM, reset must rise to VIH within 10 clocks (1.25 s at eight MHz). For appli-
cations that meet the current requirements of the SCIM’s reset timing, no apparent
change in reset timing will occur on the SCIM2E. Reset vector fetch and code execu-
tion for the SCIM2E will begin after the 10th clock as it does on the SCIM. Applications
that do not pull reset high by the end of the first 10 clocks are effectively given one
more chance to have properly released reset by the 190th clock (180 clocks after the
end of the initial 10-clock period). If reset has not been released by this time, reset is
re-asserted by the SCIM2’s reset controller for 512 clocks, reset configuration is again
latched from the data bus, and the sequence is repeated.
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
4.3 System
Clock.
MOTOROLA
4-52