MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 346

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MC68F375BGMZP33

Manufacturer Part Number
MC68F375BGMZP33
Description
IC MPU 32BIT 33MHZ 217-PBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68F375BGMZP33

Processor Type
M683xx 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
217-PBGA
Processor Series
M683xx
Core
CPU32
Data Bus Width
32 bit
Program Memory Type
Flash
Program Memory Size
256 KB
Data Ram Size
10 KB
Interface Type
SPI, SCI, CAN
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
48
Number Of Timers
16
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
No

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68F375BGMZP33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
MC68F375
REFERENCE MANUAL
The rate at which TCR1 is incremented is determined as follows:
Figure 8-2
• The PSCK and TCR1P fields in TPUMCR
• The DIV2 field in TPUMCR2
• The EPSCKE and EPSCK fields in TPUMCR3.
• The user selects either the standard prescaler (by clearing the enhanced prescal-
er enable bit, EPSCKE, in TPUMCR3) or the enhanced prescaler (by setting
EPSCKE).
— If the standard prescaler is selected (EPSCKE = 0), the the PSCK bit deter-
— If the enhanced prescaler is selected (EPSCKE = 1), the EPSCK bits select a
— The output of either the standard prescaler or the enhanced prescaler is then
— If the DIV2 bit is one, the TCR1 counter increments at a rate of the internal
mines whether the standard prescaler divides the system clock input by 32
(PSCK = 0) or four (PSCK = 1)
value by which the system clock is divided. The lowest frequency for TCR1
clock is system clock divided by 64x8. The highest frequency for TCR1 clock
is system clock divided by two (2x1). See
divided by 1, 2, 4, or 8, depending on the value of the TCR1P field in the
TPUMCR.
clock divided by two. If DIV2 is zero, the TCR1 increment rate is defined by the
output of the TCR1 prescaler (which, in turn, takes as input the output of either
the standard or enhanced prescaler).
shows a diagram of the TCR1 prescaler control block.
Table 8-1 Enhanced TCR1 Prescaler Divide Values
0x04, 0x05,...0x1d
Freescale Semiconductor, Inc.
EPSCK Value
For More Information On This Product,
Table 8-2 TCR1 Prescaler Values
0x00
0x01
0x02
0x03
0x1e
0x1f
TCR1P Value
TIME PROCESSOR UNIT 3
Go to: www.freescale.com
0b00
0b01
0b10
0b11
Rev. 25 June 03
Divide System Clock By
2
4
6
8
10,12,...60
62
64
Divide by
1
2
4
8
Table
8-1.
MOTOROLA
8-6

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