MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 288

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

6.8.7.6 Receiver Operation
MC68F375
REFERENCE MANUAL
Some serial communication systems require a mark on the TXD pin even when the
transmitter is disabled. Configure the TXD pin as an output, then write a one to either
QDTX1 or QDTX2 of the PORTQS register. See 6.6.1. When the transmitter releases
control of the TXD pin, it reverts to driving a logic one output.
To insert a delimiter between two messages, to place non-listening receivers in wake-
up mode between transmissions, or to signal a re-transmission by forcing an idle-line,
clear and then set TE before data in the serial shifter has shifted out. The transmitter
finishes the transmission, then sends a preamble. After the preamble is transmitted, if
TDRE is set, the transmitter marks idle. Otherwise, normal transmission of the next
sequence begins.
Both TDRE and TC have associated interrupts. The interrupts are enabled by the
transmit interrupt enable (TIE) and transmission complete interrupt enable (TCIE) bits
in SCCxR1. Service routines can load the last data frame in a sequence into SCxDR,
then terminate the transmission when a TDRE interrupt occurs.
Two SCI messages can be separated with minimum idle time by using a preamble of
10 bit-times (11 if a 9-bit data format is specified) of marks (logic ones). Follow these
steps:
In this sequence, if the first data frame of the second message is not transferred to
TDRx prior to the finish of the preamble transmission, then the transmit data line
(TXDx pin) marks idle (logic one) until TDRx is written. In addition, if the last data frame
of the first message finishes shifting out (including the stop bit) and TE is clear, TC
goes high and transmission is considered complete. The TXDx pin reverts to being a
general-purpose output pin.
The RE bit in SCCxR1 enables (RE = 1) and disables (RE = 0) the receiver. The
receiver contains a receive serial shifter and a parallel receive data register (RDRx)
located in the SCI data register (SCxDR). The serial shifter cannot be directly
accessed by the CPU. The receiver is double-buffered, allowing data to be held in the
RDRx while other data is shifted in.
Receiver bit processor logic drives a state machine that determines the logic level for
each bit-time. This state machine controls when the bit processor logic is to sample
the RXD pin and also controls when data is to be passed to the receive serial shifter.
A receive time clock is used to control sampling and synchronization. Data is shifted
into the receive serial shifter according to the most recent synchronization of the
receive time clock with the incoming data stream. From this point on, data movement
1. Write the last data frame of the first message to the TDRx
2. Wait for TDRE to go high, indicating that the last data frame is transferred to the
3. Clear TE and then set TE back to one. This queues the preamble to follow the
4. Write the first data frame of the second message to register TDRx
transmit serial shifter
stop bit of the current transmission immediately.
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
MOTOROLA
6-54