MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 395

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

10.6.5 Array Read Operation
10.6.6 Programming
MC68F375
REFERENCE MANUAL
cause the BIU to generate either a bus error or return all
reserved registers shall have no effect. See section
Control Block Addressing
The CMFI EEPROM array is available for read operation under most conditions while
the device is powered up. Reads of the array are not allowed during master reset, sys-
tem reset, and ACCESS = 0 while high voltage is applied to the array or while the CMFI
EEPROM is stopped, see section
stopping the CMFI EEPROM. At certain points, as defined in the program or erase
sequence, reading the array shall result in a margin read. These margin reads return
the status of the program or erase operation and not the data in the array.
After reset, programming writes, erase interlock write, setting EHV, clearing SES or
setting/clearing SIE (this affects the lower array blocks burst buffer only) the burst buff-
ers will not contain valid information and the correct information will be fetched from
the array.
Section
EEPROM are associated to array blocks. During burst read operation, the initial read
will require at least 2 clocks depending on the state of WAIT[1:0]. Subsequent burst
reads will take 1 clock until the end of the burst buffer is reached or the burst is termi-
nated by the IMB3.
To modify the charge stored in the isolated element of the CMFI bit from a logic 1 state
to a logic 0 state, a programming operation is required. This programming operation
shall apply the required voltages to change the charge state of the selected bits with-
out changing the logic state of any other bits in the CMFI array. The program operation
cannot change the logic 0 state to a logic 1 state; this transition must be done by the
erase operation. Programming uses a set of up to 8 program buffers of 64 bytes each
to store the required data, an address offset buffer to store the starting address of the
block(s) to be programmed and a block select buffer that stores information on which
block(s) are to be programmed. Any number of the array blocks may be programmed
at one time.
Do not program any page more than once after a successful erase operation. While
this will not physically damage the array it shall cause an increased partial disturb time
for the unselected bits on the row and columns that are not programmed.
A full erase of all blocks being programmed must be done before the CMFI EEPROM
can be used reliably if over programming occurs.
10.5.1 Read Burst Buffers
Freescale Semiconductor, Inc.
CDR MoneT FLASH FOR THE IMB3 (CMFI)
For More Information On This Product,
for more information on register accesses.
Go to: www.freescale.com
Rev. 25 June 03
10.6.8 Stop Operation
defines how the two burst buffers in the CMFI
10.4.1 CMFI EEPROM Module
zeros.
for more information on
Write accesses to
MOTOROLA
10-25