MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 336

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

RXGMSKHI — Receive Global Mask Register High
RXGMSKLO — Receive Global Mask Register Low
7.8.8 Receive Global Mask Registers
7.8.9 Receive Buffer 14 Mask Registers
RX14MSKHI — Receive Buffer 14 Mask Register High
RX14MSKLO — Receive Buffer 14 Mask Register Low
MC68F375
REFERENCE MANUAL
MID28 MID27 MID26 MID25 MID24 MID23 MID22 MID21 MID20 MID19 MID18
MID14 MID13 MID12 MID11 MID10 MID9
MSB
MSB
31
15
Bit(s)
Bit(s)
1
1
15:0
31:0
RESET:
RESET:
The receive buffer 14 mask registers have the same structure as the receive global
mask registers and are used to mask buffer 14.
30
14
1
1
TIMER
Name
Name
MIDx
29
13
1
1
28
12
Table 7-20 RXGMSKHI, RXGMSKLO Bit Settings
1
1
The free running timer counter can be read and written by the CPU. The timer starts from
zero after reset, counts linearly to 0xFFFF, and wraps around.
The timer is clocked by the TouCAN bit-clock. During a message, it increments by one for
each bit that is received or transmitted. When there is no message on the bus, it increments
at the nominal bit rate.
The timer value is captured at the beginning of the identifier field of any frame on the CAN
bus. The captured value is written into the “time stamp” entry in a message buffer after a suc-
cessful reception or transmission of a message.
The receive global mask registers use four bytes. The mask bits are applied to all receive-
identifiers, excluding receive-buffers 14 and 15, which have their own specific mask
registers.
Base ID mask bits MID[28:18] are used to mask standard or extended format frames.
Extended ID bits MID[17:0] are used to mask only extended format frames.
The RTR/SRR bit of a received frame is never compared to the corresponding bit in the mes-
sage buffer ID field. However, remote request frames (RTR = 1) once received, are never
stored into the message buffers. RTR mask bit locations in the mask registers (bits 20 and
0) are always zero, regardless of any write to these bits.
The IDE bit of a received frame is always compared to determine if the message contains a
standard or extended identifier. Its location in the mask registers (bit 19) is always one,
regardless of any write to this bit.
Freescale Semiconductor, Inc.
27
11
1
1
For More Information On This Product,
Table 7-19 TIMER Bit Settings
CAN 2.0B CONTROLLER MODULE
26
10
1
1
Go to: www.freescale.com
MID8
25
1
9
1
Rev. 25 June 03
MID7
24
1
8
1
MID6
23
1
7
1
Description
Description
MID5
22
1
6
1
MID4
21
1
5
1
MID3
20
0
0
4
1
MID2
19
1
1
3
1
MID17 MID16 MID15
MID1
18
1
2
1
0xYF F090
0xYF F092
0xYF F094
0xYF F096
MOTOROLA
MID0
17
1
1
1
LSB
LSB
7-30
16
1
0
0
0