MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 191

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

5.10.1 Queue Priority
MC68F375
REFERENCE MANUAL
occur for queue 1 and queue 2
Queue 1 active/trigger event
Queue 2 active/trigger event
Simultaneous trigger events
table. A queue is a scan sequence of one or more input channels. By using a pause
mechanism, subqueues can be created within the two queues. Each queue can be
operated using several different scan modes. The scan modes for queue 1 and queue
2 are programmed in QACR1 and QACR2. Once a queue has been started by a trigger
event (any of the ways to cause the QADC64 to begin executing the CCWs in a queue
or subqueue), the QADC64 performs a sequence of conversions and places the
results in the result word table.
Queue 1 has execution priority over queue 2 execution.
tions under which queue 1 asserts its priority:
Figure 5-7
queues. Queue 1 is shown with four CCWs in each subqueue and queue 2 has two
CCWs in each subqueue.
Subqueues paused
occurs for queue 2
occurs for queue 1
Queue State
Inactive
shows the CCW format and an example of using pause to create sub-
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Freescale Semiconductor, Inc.
Table 5-3 Queue 1 Priority Assertion
A trigger event for queue 1 or queue 2 causes the corresponding queue execution to
begin.
Queue 2 cannot begin execution until queue 1 reaches completion or the paused
state. The status register records the trigger event by reporting the queue 2 status as
trigger pending. Additional trigger events for queue 2, which occur before execution
can begin, are recorded as trigger overruns.
The current queue 2 conversion is aborted. The status register reports the queue 2
status as suspended. Any trigger events occurring for queue 2 while queue 2 is sus-
pended are recorded as trigger overruns. Once queue 1 reaches the completion or
the paused state, queue 2 begins executing again. The programming of the resume
bit in QACR2 determines which CCW is executed in queue 2.
Queue 1 begins execution and the queue 2 status is changed to trigger pending.
The pause feature can be used to divide queue 1 and/or queue 2 into multiple sub-
queues. A subqueue is defined by setting the pause bit in the last CCW of the sub-
queue.
For More Information On This Product,
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Rev. 25 June 03
Result
Table 5-3
shows the condi-
MOTOROLA
5-15