MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 401

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

10.6.6.3 Programming Shadow Information
MC68F375
REFERENCE MANUAL
Failure to read each page that is being programmed after each program pulse may
result in the loss of information in the CMFI EEPROM array.
While this will not physically damage the array a full erase of all blocks being pro-
grammed must be done before the CMFI EEPROM can be used reliably.
For more information see section
Programming the shadow information uses the same procedure as programming the
array except that only the program page buffer associated with the lowest array block
will be used to program the shadow information. Before starting the program sequence
SIE must be a 1.
The first 32 bytes (IADDR[7:0] = 0x00 to 0x1F) of the 256 bytes of shadow locations
are withheld by Motorola for the shadow information words and future applications.
The remaining 224 bytes are available for general use. Programming of these 32 bytes
affects the reset configuration of the CMFI EEPROM. The register shadow information
word and location within the shadow row is presented in the following table. Registers
not listed in this table do not require shadow information for reset configuration but
their shadow locations are withheld from general use by Motorola for future
applications.
Current Data in the Pro-
NOTES:
gram Page Buffer
1. 0 = bit needs to further programming
2. A “0” read during the margin read means that the bit does NOT need further programming. A “1” means
1 = bit does not need further programming
the bit needs to be programmed further.
Register Name
CMFICTL1
CMFIMCR
CMFIBAR
CMFIBS0
CMFIBS1
CMFIBS2
CMFIBS3
0
0
1
1
Table 10-14 Results of Programming Margin Read
1
Table 10-15 Register Shadow Information
Freescale Semiconductor, Inc.
CDR MoneT FLASH FOR THE IMB3 (CMFI)
For More Information On This Product,
Current State of Bit
Programmed (0)
Programmed (0)
Erased (1)
Erased (1)
Go to: www.freescale.com
Register Address
10.6.6.4 Over
Rev. 25 June 03
0x00 000C
0x00 0000
0x00 0008
0x00 0010
0x00 0012
0x00 0014
0x00 0016
Data Read During
Margin Read
Programming.
0
1
0
0
2
Shadow Row Address (addr[7:0])
Program Page Buffer
New Data for the
0x0C
0x00
0x08
0x10
0x12
0x14
0x16
1
0
1
1
MOTOROLA
1
10-31