MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 466

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

13.7 Time Base Bus System
13.7.1 Clock Selection
13.7.2 The PWMSM Counter (PWMC)
13.7.3 PWMSM Period Registers and Comparator
MC68F375
REFERENCE MANUAL
The time base bus (TBB) system makes it possible to freely configure connections
between counter submodules and action submodules. However the PWMSM sub-
modules are independent of the time base bus system. The CTM9 configuration is
shown in
The PWMSM contains an 8-bit prescaler that is clocked by the PCLK1 signal from the
CPSM (i.e. the MCU system clock divided by 2 or by 3). A 3-bit field (CLK[2:0]) in the
PWMSM status, interrupt and control register (PWMSIC) allows the software to select
which of the 8 prescaler outputs drives the PWMSM counter. The prescaler outputs
are the main MCU clock divided by: 2, 4, 8, 16, 32, 64, 128 and 512 (or 3, 6, 12, 24,
48, 96, 192 and 768, if the divide-by-3 option is used in the CPSM to generate PCLK1).
The 16-bit up-counter in the PWMSM provides the time base for the PWM output sig-
nal. The counter is held in the 0x0001 state on reset or when the PWMSM is disabled.
When the PWMSM is enabled, the counter begins counting at the rate defined by the
clock selection. Each time the counter matches the contents of the period register, the
counter is preset to 0x0001 and starts to count from that value. The counter can be
read at any time without affecting its value. Writing to the counter has no effect.
The period section of the PWMSM consists of two 16-bit period registers (PWMA1 and
PWMA2) and one 16-bit comparator. PWMA2 holds the current PWM period value and
PWMA1 holds the next PWM period value. The software establishes the next period
of the output PWM signal by writing a value into PWMA1. PWMA2 acts as a double
buffer of PWMA1, allowing the contents of PWMA1 to be changed at any time without
affecting the current period of the output signal; it cannot be accessed directly by the
software. PWMA1 can be read or written at any time. The new value in the PWMA1
register is transferred to PWMA2 on the next full cycle of the output or when a ‘1’ is
written to the LOAD bit in the PWMSIC register.
The comparator continuously compares the contents of the PWMA2 register with the
value in the PWMSM counter. When a match occurs, the state sequencer sets the out-
put flip-flop and resets the counter to 0x0001.
Period values 0x0000 and 0x0001 are special cases. When PWMA2 contains 0x0000,
an output period of 65536 PWM clock periods is generated.
When PWMA2 contains 0x0001, a period match occurs on every PWM clock period:
the counter never increments beyond 0x0001 and the output level never changes.
Figure
13-1.
Freescale Semiconductor, Inc.
For More Information On This Product,
CONFIGURABLE TIMER MODULE (CTM9)
Go to: www.freescale.com
Rev. 25 June 03
MOTOROLA
13-40