MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 380

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

CMFIMCR — CMFI EEPROM Configuration Register
MC68F375
REFERENCE MANUAL
RESET:
STOP
MSB
Bit(s)
NOTES:
15
U
15
14
2
1. The default values of some bits in the CMFIMCR are read from the location 0 of the shadow row.
2. Reset state is defined by a shadow bit or the state of D15 during reset mode configuration.
3. Reset state is defined by a shadow bit.
4. Reset state is defined by D[10] or the state of D[13] during reset mode configuration.
5. Reset state is defined by a shadow bit, bit is write protected by LOCK and STOP.
6. Reset state is defined by a shadow bit, bit is write protected by LOCK.
1
PROTECT
PROTECT
14
1
Name
STOP
SIE
13
0
Stop control. When the STOP control bit is a 1, the CMFI EEPROM array is disabled. It will
not respond to the base address stored in CMFIBAR. STOP will prevent read accesses to
the array and to the shadow information words, but has no effect on accesses to the control
registers. Attempts to read any shadow information word while STOP = 1 will produce inde-
terminate results. With STOP = 1 the CMFI may enter the lower power clock stop operation,
see
gram and erase voltage will automatically be turned off by clearing the EHV bit.
The state of this bit after master reset is the logical OR of the inverted state of D[15] and the
STOP shadow bit, STOP = D[15] or STOP shadow bit. If STOP is set to a 1 by D[15] or the
STOP shadow bit during master reset, the array may be re-enabled by clearing STOP after
master reset. This bit is read/write always.
0 = The CMFI EEPROM module is in normal mode of operation.
1 = Causes the CMFI EEPROM module to enter low power STOP operation.
Prevent array program/erase. The CMFI EEPROM array and shadow information are pro-
tected from program and erase operation by setting PROTECT = 1. The CMFI BIU will
perform all programming and erase interlocks except the program and erase voltages will
not be applied to locations within the array if PROTECT = 1
Read always, Write when LOCK = 1 and SES = 0.
0 = All NVM bits are unprotected.
1 = All NVM bits are protected.
BOOT
U
12
4.4.9 Low Power Stop
Freescale Semiconductor, Inc.
3
CDR MoneT FLASH FOR THE IMB3 (CMFI)
For More Information On This Product,
Table 10-4 CMFIMCR Bit Settings
LOCK
11
1
Go to: www.freescale.com
EMUL
10
U
4
Rev. 25 June 03
9
Mode. If STOP is set during programming or erasing, the pro-
ASPC
U
5
8
Description
7
WAIT
U
6
6
—
5
0
—
4
0
—
3
0
0xYF F800
—
2
0
MOTOROLA
—
1
0
10-10
—
0
0