MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 443

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

13.4.1.2 Input Capture (IC) Mode
13.4.1.3 Output Compare (OC) Mode
MC68F375
REFERENCE MANUAL
In IC mode, the 16-bit counter value on the selected time base bus is ‘captured’ when
a triggering event occurs on the channel’s input pin. Triggering of the input capture cir-
cuitry is done by a rising or falling edge on the input pin; the polarity of the triggering
edge is selected by the EDOUT bit. The logic level on the input pin can be read by soft-
ware via the IN bit in the channel’s SIC register.
In IC mode, the input pin is Schmitt triggered and the input signal is synchronized to
the system clock (f
being Schmitt triggered and synchronized).
When an input capture occurs, the count value on the selected time base bus is
latched into the channel’s 16-bit data register. At the same time, the FLAG bit in the
SIC register is set to indicate that an input capture has occurred.
The FLAG bit must be reset by software (see
Bits). If the interrupt is serviced, the FLAG bit should be cleared by the servicing rou-
tine before returning from that routine. If a subsequent input capture event occurs
while the FLAG bit is set, the new captured counter value is latched, and the FLAG bit
remains unchanged.
In IC mode, the value of the EDOUT bit is permanently transferred to the output flip-
flop. This value will be output on the pin when the mode is changed to one of the output
modes.
In OC mode, the state of an output pin is changed when a successful output compare
occurs; an interrupt may also be generated. The output compare circuitry performs a
comparison between the 16-bit register and the selected time base bus. When a match
is found, the EDOUT bit value is transferred to the output flip-flop. At the same time,
1. Disable SASM interrupts
2. Change mode
3. Reset the corresponding FLAG bit
4. Re-enable SASM interrupts (if desired)
To avoid spurious interrupts, and to make sure that the FLAG bit is
set according to the newly selected mode, the following sequence of
operations should be adopted when changing mode:
When changing between output modes (OP, OC or OCT), it is not
necessary to follow this procedure, as in these modes the FLAG bit
merely indicates to the software that the compare value may be
updated.
SYS
Freescale Semiconductor, Inc.
For More Information On This Product,
CONFIGURABLE TIMER MODULE (CTM9)
). The IN bit reflects the state present on the input pin (after
Go to: www.freescale.com
Rev. 25 June 03
WARNING
NOTE
13.4.1.1 Clearing and Using the FLAG
MOTOROLA
13-17