MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 603

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

EDOUT - bit in SICA 13-22
EMPTY 7-5
EMU 8-4, 8-11
Emulation
Emulation mode
Emulator chip select (CSE) 4-69
Encoded
Ending queue pointer (ENDQP) 6-19
End-of-
End-of-queue condition 5-47
ENDQP 6-19, 6-24
Entry
EOF 7-16
EOQ 5-17
ERRINT 7-32
Error
ESTAT 7-31
ETBANK 8-19
ETRIG 5-5
event counter
Event timing 8-3
Exception
EXT 4-56
EXTAL 4-57, 4-69
Extended message format 7-1
External
Externally
MC68F375
REFERENCE MANUAL
control (EMU) 8-11
support 8-4
selection 4-69
one of three channel priority levels (CH) 8-17
time function for each channel (CHANNEL) 8-15
type of host service (CH) 8-17
frame (EOF) 7-16
table bank select field (ETBANK) 8-19
conditions 6-55
counters 7-9
interrupt (ERRINT) 7-32
FCSM 13-6
MCSM 13-11
instruction (RTE) 4-49
processing 3-16, 4-55
vector 4-55, 8-5
frames 7-5
bus
clock input timing diagram E-9
digital supply pin 5-6
multiplexing 5-9
reset (EXT) 4-56
trigger pins 5-5
trigger single-scan mode 5-20
multiplexed mode (MUX) 5-38
sequence 3-18
types of exceptions 3-18
vectors 3-16
arbitration 4-50
interface (EBI) 4-1, 4-31
exception vector assignments 3-17
bus control signals 4-32
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
INDEX
FAR 3-23
Fast
Fast quadrature decode TPU function (FQD) D-28
FASTREF 4-6, 4-60
Fault confinement state (FCS) 7-10, 7-32
FC 4-34
FCS 7-10, 7-32
FCSM
FCSMCNT 13-9
FCSMSIC 13-7
FE 6-49, 6-55
Final sample time 5-12
FLAG
FORCE - bit in SICA 13-21
FORMERR 7-31
FPSCK 8-19
F
FQD D-28
FQM D-10
Frame 6-50
Frames
Framing error (FE) flag 6-49, 6-55
FREEZ ACK 7-17
FREEZE
QCLK
termination
termination cycles 4-38, 4-41
parameters
block diagram 13-5
clock sources 13-6
counter 13-5
counter overflow 13-8
counter register 13-9
driving the time base bus 13-8
effect of reset 13-5
event counter 13-6
flag clearing 13-8
freeze 13-6
input pin - CTMC 13-6, 13-8
interrupts 13-6
maximum external clock frequency 13-6, 13-8
registers
reserved registers 13-7
selecting the clock source 13-8
setting the interrupt level 13-8, 13-36
using multiple FCSMs 13-7
bit in DASMSIC 13-36
bit in SICA 13-21
size 6-55
overload 7-16
remote 7-16
assertion response (FRZ)
5-25
read cycle timing diagram E-12
write cycle timing diagram E-13
primary channel D-29
secondary channel D-30
status/interrupt
QADC 5-7, 5-35, 11-4
control register (FCSMSIC) 13-7
–F–
MOTOROLA
Index-5