MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 107

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.4.2 Reset Status
4.4.3 Bus Monitor
4.4.4 Halt Monitor
MC68F375
REFERENCE MANUAL
Bit(s)
1:0
3
2
The reset status register (RSR) latches MCU status during reset. Refer to
Status Register
The internal bus monitor checks data size acknowledge (DSACK) or autovector
(AVEC) signal response times during normal bus cycles. The monitor asserts the inter-
nal bus error (BERR) signal when the response time is excessively long.
DSACK and AVEC response times are measured in clock cycles. Maximum allowable
response time can be selected by setting the bus monitor timing (BMT[1:0]) field in the
system protection control register (SYPCR).
The monitor does not check DSACK response on the external bus unless the CPU32
initiates a bus cycle. The BME bit in SYPCR enables the internal bus monitor for inter-
nal-to-external bus cycles. If a system contains external bus masters, an external bus
monitor must be implemented and the internal-to-external bus monitor option must be
disabled.
When monitoring transfers to an 8-bit port, the bus monitor does not reset until both
byte accesses of a word transfer are completed. Monitor timeout period must be at
least twice the number of clocks that a single-byte access requires.
The halt monitor responds to an assertion of the HALT signal on the internal bus when
a double bus fault occurs. A flag in the reset status register (RSR) will indicate when
the last reset was caused by the halt monitor. Halt monitor reset can be inhibited by
Name
HME
BME
BMT
0 = Halt monitor is disabled.
1 = Halt monitor is enabled.
Bus monitor external enable
0 = Disable bus monitor for external bus cycles.
1 = Enable bus monitor for external bus cycles.
BMT[1:0] — Bus Monitor Timing. This field selects the bus monitor timeout period. Refer to
ble
Halt monitor enable
Table 4-9 SYPCR Bit Descriptions (Continued)
4-10.
for more information.
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
BMT[1:0]
For More Information On This Product,
00
01
10
11
Table 4-10 Bus Monitor Period
Go to: www.freescale.com
Rev. 25 June 03
Bus Monitor Timeout Period
64 System Clocks
32 System Clocks
16 System Clocks
8 System Clocks
Table 4-10
Description
shows the periods allowed.
4.7.4 Reset
MOTOROLA
4-25
Ta-