MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 225

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
Bit(s)
15:10
7:6
5:0
9
8
CHAN
Name
BYP
IST
—
P
Reserved
Pause. The pause bit allows the creation of sub-queues within queue 1 and queue 2. The
QADC64 performs the conversion specified by the CCW with the pause bit set, and then the
queue enters the pause state. Another trigger event causes execution to continue from the pause
to the next CCW.
0 = Do not enter the pause state after execution of the current CCW.
1 = Enter the pause state after execution of the current CCW.
Sample amplifier bypass. Setting BYP enables the amplifier bypass mode for a conversion, and
subsequently changes the timing. Refer to
for more information.
0 = Amplifier bypass mode disabled.
1 = Amplifier bypass mode enabled.
permit more accurate A/D conversions of signals with higher source impedances, especially if
BYP=1.
00 = QCKL period x 2
01 = QCKL period x 4
10 = QCKL period x 8
11 = QCKL period x 16
input pin to be sampled and converted. The analog input pin channel number assignments and
the pin definitions vary depending on whether the QADC64 is operating in multiplexed or non-
multiplexed mode. The queue scan mechanism sees no distinction between an internally or
externally multiplexed analog input.
If CHAN specifies a reserved channel number (channels 32 to 47) or an invalid channel number
(channels 4 to 31 in non-multiplexed mode), the low reference level (V
ming the channel field to channel 63 indicates the end of the queue. Channels 60 to 62 are
special internal channels. When one of these channels is selected, the sample amplifier is not
used. The value of V
the input sample time to any value other than two for one of the internal channels has no benefit
except to lengthen the overall conversion time.
Table 5-20
shows the channel number assignments for the multiplexed mode.
Input sample time. The IST field specifies the length of the sample window. Longer sample times
Channel number. The CHAN field selects the input channel number corresponding to the analog
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Freescale Semiconductor, Inc.
For More Information On This Product,
shows the channel number assignments for the non-multiplexed mode.
Table 5-19 CCW Bit Settings
RL
Go to: www.freescale.com
, V
RH
Rev. 25 June 03
, or (V
RH
– V
RL
Description
5.9.1.1 Amplifier Bypass Mode Conversion Timing
)/2 is placed directly into the converter. Programming
RL
) is converted. Program-
MOTOROLA
Table 5-21
5-49