MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 70

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

3.9 Exception Processing
3.9.1 Exception Vectors
MC68F375
REFERENCE MANUAL
The loop mode is entered when the DBcc instruction is executed, and the loop dis-
placement is –4. Once in loop mode, the processor performs only the data cycles
associated with the instruction and suppresses all instruction fetches. The termination
condition and count are checked after each execution of the data operations of the
looped instruction. The CPU32 automatically exits the loop mode on interrupts or other
exceptions. All single word instructions that do not cause a change of flow can be
looped.
An exception is a special condition that preempts normal processing. Exception pro-
cessing is the transition from normal mode program execution to execution of a routine
that deals with an exception.
An exception vector is the address of a routine that handles an exception. The vector
base register (VBR) contains the base address of a 1024-byte exception vector table
which consists of 256 exception vectors. Sixty-four vectors are defined by the
processor and 192 vectors are reserved for user definition as interrupt vectors. Except
for the reset vector each vector in the table is one long word in length. The reset vector
is two long words in length. Refer to
All exception vectors, except the reset vector and stack pointer, are located in super-
visor data space. The reset vector and stack pointer are located in supervisor program
space. Only the initial reset vector and stack pointer are fixed in the processor memory
map. When initialization is complete, there are no fixed assignments. Since the VBR
stores the vector table base address, the table can be located anywhere in memory.
It can also be dynamically relocated for each task executed by an operating system.
Because there is no protection on the 64 processor-defined vectors,
external devices can access vectors reserved for internal purposes.
This practice is strongly discouraged.
Figure 3-7 Loop Mode Instruction Sequence
Freescale Semiconductor, Inc.
For More Information On This Product,
CENTRAL PROCESSOR UNIT
Go to: www.freescale.com
ONE WORD INSTRUCTION
DBCC DISPLACEMENT
Rev. 25 June 03
0xFFFC = – 4
Table 3-3
DBCC
CAUTION
for information on vector assignment.
1126A
MOTOROLA
3-16