MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 468

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

13.7.6 PWMSM Coherency
13.7.7 PWMSM Interrupts
13.7.8 Freeze Action on the PWMSM
13.7.9 PWM frequency, Pulse Width and Resolution
MC68F375
REFERENCE MANUAL
When using the PWM output signal to generate analog levels, the 0% and 100%
pulses provide the full scale values.
Even when 0% or 100% pulses are being generated, the 16-bit PWM counter contin-
ues to count and output changes to or from these limit values are done synchronously
with the selected period.
Byte access of registers is discussed in
should be noted that byte writes to the double buffered registers PWMA1 and PWMB1
are not recommended as the transfer from the primary registers to the secondary reg-
isters is done on a word basis.
For most PWMSM operations, 16-bit accesses are sufficient and long word accesses
are treated as two word accesses, with one exception — a long word write to the
period/pulse width registers. In this case, if the long word write is done within the PWM
period, there is no visible effect on the output signal and the new values are stored in
PWMA1 and PWMB1 ready to be loaded into the buffer registers at the start of the next
period. If, however, the long word write coincides with the end of the period, then the
transfer of values from the primary registers to the secondary registers is suppressed
until the end of the next PWM period; during this period, the current values in the sec-
ondary registers are used for the period and the pulse width.
The FLAG bit in the PWMSIC register is set when a new period begins and indicates
that the period and pulse width registers (PWMA1 and PWMB1) may be updated with
values for the next output period and pulse width. When the FLAG bit is set, an inter-
rupt request is generated on one of eight levels as defined by the interrupt level bits
(IL[2:0]) in the PWMSIC register. If the interrupt level is set to zero, interrupts are
disabled.
When the IMB FREEZE signal is recognized, the PWMSM counter stops incrementing
and remains set at its last value. When the FREEZE signal is negated, the counter
starts incrementing from its last value, as if nothing had happened.
Table 13-12
achieved using the /2 and /3 options and a clock frequency of 16.78 MHz.
and
Table 13-13
Freescale Semiconductor, Inc.
For More Information On This Product,
CONFIGURABLE TIMER MODULE (CTM9)
Go to: www.freescale.com
shows the pulse widths and frequencies that can be
Rev. 25 June 03
13.5.1 32-Bit Coherent
Access, however, it
MOTOROLA
13-42