MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 86

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.2.2 Module Mapping
4.2.3 Interrupt Arbitration
4.2.4 Noise Reduction in Single-Chip Mode
MC68F375
REFERENCE MANUAL
Mnemonic
Control registers for all the modules in the microcontroller are mapped into a 4-Kbyte
block. The state of the module mapping (MM) bit in SCIMMCR determines where the
control register block is located in the system memory map. When MM = 0, register
addresses range from 0x7FF000 to 0x7FFFFF; when MM = 1, register addresses
range from 0xFFF000 to 0xFFFFFF.
For CPU16 devices, the MM bit must be a logical in order for the internal registers to
be available. The MM bit is a write-once bit. Writing the M bit to a logic 0 will make the
internal registers unavailable until a system reset occurs.
Each module that can request interrupts has an interrupt arbitration (IARB) field. Arbi-
tration between interrupt requests of the same priority is performed by serial
contention between IARB field bit values. Contention will take place whenever an inter-
rupt request is acknowledged, even when there is only a single request pending. For
an interrupt to be serviced, the appropriate IARB field must have a non-zero value. If
an interrupt request from a module with an IARB field value of 0b0000 is recognized,
the CPU32 will start to process the interrupt. The CPU will attempt to run and IACK
cycle. Because the IARB values of the interrupting module is 0b0000, the module can-
not cause the termination of the IACK cycle. In this case, the IACK cycle can only be
terminated by an external DSACK, a software watchdog timeout or a bus error. If the
IACK cycle is terminated by BERR, a spurious interrupt exception is taken.
Because the SCIM2E routes external interrupt requests to the CPU32, the SCIM2E
IARB field value is used for external interrupts. The reset value of IARB for the
SCIM2E is 0b1111. The reset IARB value for all other modules is 0b0000. This pre-
vents SCIM2E interrupts from being discarded during initialization. Refer to
Interrupts
Four bits in SCIMMCR control pins that can be disabled in single-chip mode to reduce
MCU noise emissions. The characteristics of these control bits are listed in
Except for EXOFF, these bits disable their associated pins when the MCU is config-
ured for single-chip mode (BERR = 0 during reset).
EXOFF
CPUD
RWD
ABD
Bit
for a discussion of interrupt arbitration.
Position in
SCIMMCR
15
12
5
4
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
Table 4-2 SCIMMCR Noise Control Bits
For More Information On This Product,
Disables CLKOUT when set to one.
Disables IPIPE/DSO and IFETCH/DSI pins when set to one.
Disables ADDR[2:0] when set to one.
Disables R/W when set to one.
Go to: www.freescale.com
Rev. 25 June 03
Function
Inverted state of
the BERR pin
Reset State
MOTOROLA
Table
0
4-2.
4.8
4-4